[PATCH 0/4] PCI: dwc: pci-dra7: Support PCIe x2 lane mode

[PATCH 0/4] PCI: dwc: pci-dra7: Support PCIe x2 lane mode

[Kishon Vijay Abraham I]

Patch series adds support to enable x2 lane mode in dra74/dra76
based boards in pci-dra7xx driver. It introduces new compatible strings
in order to enable x2 lane mode support.

x2 lane mode support for dra72 based boards will be added in a later
series.

patch series is created on top of https://lkml.org/lkml/2017/10/9/133.

Kishon Vijay Abraham I (4):
  dt-bindings: PCI: dra7xx: Add SoC specific compatible strings
  dt-bindings: PCI: dra7xx: Add properties to enable x2 lane in dra7
  PCI: dwc: dra7xx: Add support for SoC specific compatible strings
  PCI: dwc: pci-dra7xx: Enable x2 mode support

 Documentation/devicetree/bindings/pci/ti-pci.txt | 12 +++-
 drivers/pci/dwc/pci-dra7xx.c                     | 80 ++++++++++++++++++++++++
 2 files changed, 90 insertions(+), 2 deletions(-)

-- 
2.11.0

[PATCH 1/4] dt-bindings: PCI: dra7xx: Add SoC specific compatible strings

[Kishon Vijay Abraham I]

Add new compatible strings for dra74x SoC (also used by dra76x) and
dra72x. This can be used to perform SoC specific configuration
(like configuring PCIe in x2 lane mode).

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
 Documentation/devicetree/bindings/pci/ti-pci.txt | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt
index 7f7af3044016..82cb875e4cec 100644
--- a/Documentation/devicetree/bindings/pci/ti-pci.txt
+++ b/Documentation/devicetree/bindings/pci/ti-pci.txt
@@ -1,8 +1,12 @@
 TI PCI Controllers
 
 PCIe DesignWare Controller
- - compatible: Should be "ti,dra7-pcie" for RC
-	       Should be "ti,dra7-pcie-ep" for EP
+ - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
+	       Should be "ti,dra7-pcie-ep" for EP (deprecated)
+	       Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
+	       Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
+	       Should be "ti,dra726-pcie-rc" for dra72x in RC mode
+	       Should be "ti,dra726-pcie-ep" for dra72x in EP mode
  - phys : list of PHY specifiers (used by generic PHY framework)
  - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
 	       number of PHYs as specified in *phys* property.
-- 
2.11.0

Re: [PATCH 1/4] dt-bindings: PCI: dra7xx: Add SoC specific compatible strings

[Rob Herring]

On Tue, Oct 10, 2017 at 03:46:03PM +0530, Kishon Vijay Abraham I wrote:
> Add new compatible strings for dra74x SoC (also used by dra76x) and
> dra72x. This can be used to perform SoC specific configuration
> (like configuring PCIe in x2 lane mode).
> 
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
> ---
>  Documentation/devicetree/bindings/pci/ti-pci.txt | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)

Acked-by: Rob Herring <robh@kernel.org>

[PATCH 2/4] dt-bindings: PCI: dra7xx: Add properties to enable x2 lane in dra7

[Kishon Vijay Abraham I]

Add syscon properties required for configuring PCIe in x2 lane mode.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
 Documentation/devicetree/bindings/pci/ti-pci.txt | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt
index 82cb875e4cec..455cb74a475c 100644
--- a/Documentation/devicetree/bindings/pci/ti-pci.txt
+++ b/Documentation/devicetree/bindings/pci/ti-pci.txt
@@ -13,6 +13,10 @@ PCIe DesignWare Controller
  - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
 	       where <X> is the instance number of the pcie from the HW spec.
  - num-lanes as specified in ../designware-pcie.txt
+ - syscon-lane-conf : phandle/offset pair. Phandle to the system control module and the
+   register offset to specify 1 lane or 2 lane.
+ - syscon-lane-sel : phandle/offset pair. Phandle to the system control module and the
+   register offset to specify lane selection.
 
 HOST MODE
 =========
-- 
2.11.0

Re: [PATCH 2/4] dt-bindings: PCI: dra7xx: Add properties to enable x2 lane in dra7

[Rob Herring]

On Tue, Oct 10, 2017 at 03:46:04PM +0530, Kishon Vijay Abraham I wrote:
> Add syscon properties required for configuring PCIe in x2 lane mode.
> 
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
> ---
>  Documentation/devicetree/bindings/pci/ti-pci.txt | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt
> index 82cb875e4cec..455cb74a475c 100644
> --- a/Documentation/devicetree/bindings/pci/ti-pci.txt
> +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt
> @@ -13,6 +13,10 @@ PCIe DesignWare Controller
>   - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
>  	       where <X> is the instance number of the pcie from the HW spec.
>   - num-lanes as specified in ../designware-pcie.txt
> + - syscon-lane-conf : phandle/offset pair. Phandle to the system control module and the
> +   register offset to specify 1 lane or 2 lane.
> + - syscon-lane-sel : phandle/offset pair. Phandle to the system control module and the
> +   register offset to specify lane selection.

Needs vendor prefixes.

Rob

[PATCH 3/4] PCI: dwc: dra7xx: Add support for SoC specific compatible strings

[Kishon Vijay Abraham I]

dra74x/dra76x and dra72x has separate compatible strings. Add support
for these compatible strings in pci-dra7xx driver.

This is a preparatory patch for adding 2-lane mode support and
dra74/dra72 should add it's own driver data for 2-lane mode
configuration.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
 drivers/pci/dwc/pci-dra7xx.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
index 362607f727ee..78a87a8f1362 100644
--- a/drivers/pci/dwc/pci-dra7xx.c
+++ b/drivers/pci/dwc/pci-dra7xx.c
@@ -542,6 +542,22 @@ static const struct of_device_id of_dra7xx_pcie_match[] = {
 		.compatible = "ti,dra7-pcie-ep",
 		.data = &dra7xx_pcie_ep_of_data,
 	},
+	{
+		.compatible = "ti,dra746-pcie-rc",
+		.data = &dra7xx_pcie_rc_of_data,
+	},
+	{
+		.compatible = "ti,dra746-pcie-ep",
+		.data = &dra7xx_pcie_ep_of_data,
+	},
+	{
+		.compatible = "ti,dra726-pcie-rc",
+		.data = &dra7xx_pcie_rc_of_data,
+	},
+	{
+		.compatible = "ti,dra726-pcie-ep",
+		.data = &dra7xx_pcie_ep_of_data,
+	},
 	{},
 };
 
-- 
2.11.0

Re: [PATCH 3/4] PCI: dwc: dra7xx: Add support for SoC specific compatible strings

[Bjorn Helgaas]

s/PCI: dwc: dra7xx: Add support for SoC specific compatible strings/
  PCI: dra7xx: Add dra726 and dra746 compatible strings/
  
I think including "dwc" makes sense for things that involve the DW
core, but this is really dra7xx-specific.  And I think the *support*
for SoC-specific strings was already there; it looks like this patch
simply adds some of those strings.

On Tue, Oct 10, 2017 at 03:46:05PM +0530, Kishon Vijay Abraham I wrote:
> dra74x/dra76x and dra72x has separate compatible strings. Add support
> for these compatible strings in pci-dra7xx driver.

s/has separate/have separate/

> This is a preparatory patch for adding 2-lane mode support and
> dra74/dra72 should add it's own driver data for 2-lane mode
> configuration.

s/it's/its/

> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
> ---
>  drivers/pci/dwc/pci-dra7xx.c | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
> index 362607f727ee..78a87a8f1362 100644
> --- a/drivers/pci/dwc/pci-dra7xx.c
> +++ b/drivers/pci/dwc/pci-dra7xx.c
> @@ -542,6 +542,22 @@ static const struct of_device_id of_dra7xx_pcie_match[] = {
>  		.compatible = "ti,dra7-pcie-ep",
>  		.data = &dra7xx_pcie_ep_of_data,
>  	},
> +	{
> +		.compatible = "ti,dra746-pcie-rc",
> +		.data = &dra7xx_pcie_rc_of_data,
> +	},
> +	{
> +		.compatible = "ti,dra746-pcie-ep",
> +		.data = &dra7xx_pcie_ep_of_data,
> +	},
> +	{
> +		.compatible = "ti,dra726-pcie-rc",
> +		.data = &dra7xx_pcie_rc_of_data,
> +	},
> +	{
> +		.compatible = "ti,dra726-pcie-ep",
> +		.data = &dra7xx_pcie_ep_of_data,
> +	},
>  	{},
>  };
>  
> -- 
> 2.11.0
> 

[PATCH 4/4] PCI: dwc: pci-dra7xx: Enable x2 mode support

[Kishon Vijay Abraham I]

Perform syscon configurations to get x2 mode to working in dra74x
(and dra76x).

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
 drivers/pci/dwc/pci-dra7xx.c | 68 ++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 66 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
index 78a87a8f1362..a43c904310f3 100644
--- a/drivers/pci/dwc/pci-dra7xx.c
+++ b/drivers/pci/dwc/pci-dra7xx.c
@@ -21,6 +21,7 @@
 #include <linux/of_device.h>
 #include <linux/of_gpio.h>
 #include <linux/of_pci.h>
+#include <linux/of_platform.h>
 #include <linux/pci.h>
 #include <linux/phy/phy.h>
 #include <linux/platform_device.h>
@@ -83,6 +84,9 @@
 #define MSI_REQ_GRANT					BIT(0)
 #define MSI_VECTOR_SHIFT				7
 
+#define PCIE_1LANE_2LANE_SELECTION			BIT(13)
+#define PCIE_B1C0_MODE_SEL				BIT(2)
+
 struct dra7xx_pcie {
 	struct dw_pcie		*pci;
 	void __iomem		*base;		/* DT ti_conf */
@@ -95,6 +99,10 @@ struct dra7xx_pcie {
 
 struct dra7xx_pcie_of_data {
 	enum dw_pcie_device_mode mode;
+	u32 b1co_mode_sel_mask;
+};
+
+struct dra7xx_pcie_data {
 };
 
 #define to_dra7xx_pcie(x)	dev_get_drvdata((x)->dev)
@@ -533,6 +541,16 @@ static const struct dra7xx_pcie_of_data dra7xx_pcie_ep_of_data = {
 	.mode = DW_PCIE_EP_TYPE,
 };
 
+static const struct dra7xx_pcie_of_data dra746_pcie_rc_of_data = {
+	.b1co_mode_sel_mask = BIT(2),
+	.mode = DW_PCIE_RC_TYPE,
+};
+
+static const struct dra7xx_pcie_of_data dra746_pcie_ep_of_data = {
+	.b1co_mode_sel_mask = BIT(2),
+	.mode = DW_PCIE_EP_TYPE,
+};
+
 static const struct of_device_id of_dra7xx_pcie_match[] = {
 	{
 		.compatible = "ti,dra7-pcie",
@@ -544,11 +562,11 @@ static const struct of_device_id of_dra7xx_pcie_match[] = {
 	},
 	{
 		.compatible = "ti,dra746-pcie-rc",
-		.data = &dra7xx_pcie_rc_of_data,
+		.data = &dra746_pcie_rc_of_data,
 	},
 	{
 		.compatible = "ti,dra746-pcie-ep",
-		.data = &dra7xx_pcie_ep_of_data,
+		.data = &dra746_pcie_ep_of_data,
 	},
 	{
 		.compatible = "ti,dra726-pcie-rc",
@@ -603,6 +621,44 @@ static int dra7xx_pcie_ep_unaligned_memaccess(struct device *dev)
 	return ret;
 }
 
+static int dra7xx_pcie_configure_two_lane(struct device *dev,
+					  u32 b1co_mode_sel_mask)
+{
+	struct device_node *np = dev->of_node;
+	struct regmap *pcie_syscon;
+	unsigned int pcie_reg;
+
+	pcie_syscon = syscon_regmap_lookup_by_phandle(np, "syscon-lane-conf");
+	if (IS_ERR(pcie_syscon)) {
+		dev_err(dev, "unable to get syscon-lane-conf\n");
+		return -EINVAL;
+	}
+
+	if (of_property_read_u32_index(np, "syscon-lane-conf", 1, &pcie_reg)) {
+		dev_err(dev, "couldn't get lane configuration reg offset\n");
+		return -EINVAL;
+	}
+
+	regmap_update_bits(pcie_syscon, pcie_reg, PCIE_1LANE_2LANE_SELECTION,
+			   PCIE_1LANE_2LANE_SELECTION);
+
+	pcie_syscon = syscon_regmap_lookup_by_phandle(np, "syscon-lane-sel");
+	if (IS_ERR(pcie_syscon)) {
+		dev_err(dev, "unable to get syscon-lane-sel\n");
+		return -EINVAL;
+	}
+
+	if (of_property_read_u32_index(np, "syscon-lane-sel", 1, &pcie_reg)) {
+		dev_err(dev, "couldn't get lane selection reg offset\n");
+		return -EINVAL;
+	}
+
+	regmap_update_bits(pcie_syscon, pcie_reg, b1co_mode_sel_mask,
+			   PCIE_B1C0_MODE_SEL);
+
+	return 0;
+}
+
 static int __init dra7xx_pcie_probe(struct platform_device *pdev)
 {
 	u32 reg;
@@ -624,6 +680,7 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
 	const struct of_device_id *match;
 	const struct dra7xx_pcie_of_data *data;
 	enum dw_pcie_device_mode mode;
+	u32 b1co_mode_sel_mask;
 
 	match = of_match_device(of_match_ptr(of_dra7xx_pcie_match), dev);
 	if (!match)
@@ -631,6 +688,7 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
 
 	data = (struct dra7xx_pcie_of_data *)match->data;
 	mode = (enum dw_pcie_device_mode)data->mode;
+	b1co_mode_sel_mask = data->b1co_mode_sel_mask;
 
 	dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL);
 	if (!dra7xx)
@@ -689,6 +747,12 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
 	dra7xx->pci = pci;
 	dra7xx->phy_count = phy_count;
 
+	if (phy_count == 2) {
+		ret = dra7xx_pcie_configure_two_lane(dev, b1co_mode_sel_mask);
+		if (ret < 0)
+			goto err_link;
+	}
+
 	ret = dra7xx_pcie_enable_phy(dra7xx);
 	if (ret) {
 		dev_err(dev, "failed to enable phy\n");
-- 
2.11.0

Re: [PATCH 4/4] PCI: dwc: pci-dra7xx: Enable x2 mode support

[Bjorn Helgaas]

s/PCI: dwc: pci-dra7xx: Enable x2 mode support/
  PCI: dra7xx: Enable x2 mode support for dra74x and dra76x/

Looks OK to me otherwise, but Rob had a comment about the DT names, so
I'll wait for that resolution.

On Tue, Oct 10, 2017 at 03:46:06PM +0530, Kishon Vijay Abraham I wrote:
> Perform syscon configurations to get x2 mode to working in dra74x
> (and dra76x).
> 
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
> ---
>  drivers/pci/dwc/pci-dra7xx.c | 68 ++++++++++++++++++++++++++++++++++++++++++--
>  1 file changed, 66 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
> index 78a87a8f1362..a43c904310f3 100644
> --- a/drivers/pci/dwc/pci-dra7xx.c
> +++ b/drivers/pci/dwc/pci-dra7xx.c
> @@ -21,6 +21,7 @@
>  #include <linux/of_device.h>
>  #include <linux/of_gpio.h>
>  #include <linux/of_pci.h>
> +#include <linux/of_platform.h>
>  #include <linux/pci.h>
>  #include <linux/phy/phy.h>
>  #include <linux/platform_device.h>
> @@ -83,6 +84,9 @@
>  #define MSI_REQ_GRANT					BIT(0)
>  #define MSI_VECTOR_SHIFT				7
>  
> +#define PCIE_1LANE_2LANE_SELECTION			BIT(13)
> +#define PCIE_B1C0_MODE_SEL				BIT(2)
> +
>  struct dra7xx_pcie {
>  	struct dw_pcie		*pci;
>  	void __iomem		*base;		/* DT ti_conf */
> @@ -95,6 +99,10 @@ struct dra7xx_pcie {
>  
>  struct dra7xx_pcie_of_data {
>  	enum dw_pcie_device_mode mode;
> +	u32 b1co_mode_sel_mask;
> +};
> +
> +struct dra7xx_pcie_data {
>  };
>  
>  #define to_dra7xx_pcie(x)	dev_get_drvdata((x)->dev)
> @@ -533,6 +541,16 @@ static const struct dra7xx_pcie_of_data dra7xx_pcie_ep_of_data = {
>  	.mode = DW_PCIE_EP_TYPE,
>  };
>  
> +static const struct dra7xx_pcie_of_data dra746_pcie_rc_of_data = {
> +	.b1co_mode_sel_mask = BIT(2),
> +	.mode = DW_PCIE_RC_TYPE,
> +};
> +
> +static const struct dra7xx_pcie_of_data dra746_pcie_ep_of_data = {
> +	.b1co_mode_sel_mask = BIT(2),
> +	.mode = DW_PCIE_EP_TYPE,
> +};
> +
>  static const struct of_device_id of_dra7xx_pcie_match[] = {
>  	{
>  		.compatible = "ti,dra7-pcie",
> @@ -544,11 +562,11 @@ static const struct of_device_id of_dra7xx_pcie_match[] = {
>  	},
>  	{
>  		.compatible = "ti,dra746-pcie-rc",
> -		.data = &dra7xx_pcie_rc_of_data,
> +		.data = &dra746_pcie_rc_of_data,
>  	},
>  	{
>  		.compatible = "ti,dra746-pcie-ep",
> -		.data = &dra7xx_pcie_ep_of_data,
> +		.data = &dra746_pcie_ep_of_data,
>  	},
>  	{
>  		.compatible = "ti,dra726-pcie-rc",
> @@ -603,6 +621,44 @@ static int dra7xx_pcie_ep_unaligned_memaccess(struct device *dev)
>  	return ret;
>  }
>  
> +static int dra7xx_pcie_configure_two_lane(struct device *dev,
> +					  u32 b1co_mode_sel_mask)
> +{
> +	struct device_node *np = dev->of_node;
> +	struct regmap *pcie_syscon;
> +	unsigned int pcie_reg;
> +
> +	pcie_syscon = syscon_regmap_lookup_by_phandle(np, "syscon-lane-conf");
> +	if (IS_ERR(pcie_syscon)) {
> +		dev_err(dev, "unable to get syscon-lane-conf\n");
> +		return -EINVAL;
> +	}
> +
> +	if (of_property_read_u32_index(np, "syscon-lane-conf", 1, &pcie_reg)) {
> +		dev_err(dev, "couldn't get lane configuration reg offset\n");
> +		return -EINVAL;
> +	}
> +
> +	regmap_update_bits(pcie_syscon, pcie_reg, PCIE_1LANE_2LANE_SELECTION,
> +			   PCIE_1LANE_2LANE_SELECTION);
> +
> +	pcie_syscon = syscon_regmap_lookup_by_phandle(np, "syscon-lane-sel");
> +	if (IS_ERR(pcie_syscon)) {
> +		dev_err(dev, "unable to get syscon-lane-sel\n");
> +		return -EINVAL;
> +	}
> +
> +	if (of_property_read_u32_index(np, "syscon-lane-sel", 1, &pcie_reg)) {
> +		dev_err(dev, "couldn't get lane selection reg offset\n");
> +		return -EINVAL;
> +	}
> +
> +	regmap_update_bits(pcie_syscon, pcie_reg, b1co_mode_sel_mask,
> +			   PCIE_B1C0_MODE_SEL);
> +
> +	return 0;
> +}
> +
>  static int __init dra7xx_pcie_probe(struct platform_device *pdev)
>  {
>  	u32 reg;
> @@ -624,6 +680,7 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
>  	const struct of_device_id *match;
>  	const struct dra7xx_pcie_of_data *data;
>  	enum dw_pcie_device_mode mode;
> +	u32 b1co_mode_sel_mask;
>  
>  	match = of_match_device(of_match_ptr(of_dra7xx_pcie_match), dev);
>  	if (!match)
> @@ -631,6 +688,7 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
>  
>  	data = (struct dra7xx_pcie_of_data *)match->data;
>  	mode = (enum dw_pcie_device_mode)data->mode;
> +	b1co_mode_sel_mask = data->b1co_mode_sel_mask;
>  
>  	dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL);
>  	if (!dra7xx)
> @@ -689,6 +747,12 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
>  	dra7xx->pci = pci;
>  	dra7xx->phy_count = phy_count;
>  
> +	if (phy_count == 2) {
> +		ret = dra7xx_pcie_configure_two_lane(dev, b1co_mode_sel_mask);
> +		if (ret < 0)
> +			goto err_link;
> +	}
> +
>  	ret = dra7xx_pcie_enable_phy(dra7xx);
>  	if (ret) {
>  		dev_err(dev, "failed to enable phy\n");
> -- 
> 2.11.0
>