From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757334AbdJKLyR (ORCPT ); Wed, 11 Oct 2017 07:54:17 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:56862 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752197AbdJKLyM (ORCPT ); Wed, 11 Oct 2017 07:54:12 -0400 Date: Wed, 11 Oct 2017 13:54:10 +0200 From: Boris Brezillon To: Eric Anholt Cc: dri-devel@lists.freedesktop.org, Archit Taneja , Andrzej Hajda , Laurent Pinchart , Thierry Reding , linux-kernel@vger.kernel.org Subject: Re: [PATCH v6 1/5] drm/vc4: Move the DSI clock divider workaround closer to the clock call. Message-ID: <20171011135410.3d887249@bbrezillon> In-Reply-To: <20170815234722.20700-1-eric@anholt.net> References: <20170815234722.20700-1-eric@anholt.net> X-Mailer: Claws Mail 3.14.1 (GTK+ 2.24.31; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 15 Aug 2017 16:47:18 -0700 Eric Anholt wrote: > We want the adjusted_mode->clock to be the actual clock we're > expecting to program, so that consumers see the right values for clock > and vrefresh. > > Signed-off-by: Eric Anholt Reviewed-by: Boris Brezillon > --- > drivers/gpu/drm/vc4/vc4_dsi.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/vc4/vc4_dsi.c b/drivers/gpu/drm/vc4/vc4_dsi.c > index d1e0dc908048..eb787eed8abe 100644 > --- a/drivers/gpu/drm/vc4/vc4_dsi.c > +++ b/drivers/gpu/drm/vc4/vc4_dsi.c > @@ -859,11 +859,7 @@ static bool vc4_dsi_encoder_mode_fixup(struct drm_encoder *encoder, > pll_clock = parent_rate / divider; > pixel_clock_hz = pll_clock / dsi->divider; > > - /* Round up the clk_set_rate() request slightly, since > - * PLLD_DSI1 is an integer divider and its rate selection will > - * never round up. > - */ > - adjusted_mode->clock = pixel_clock_hz / 1000 + 1; > + adjusted_mode->clock = pixel_clock_hz / 1000; > > /* Given the new pixel clock, adjust HFP to keep vrefresh the same. */ > adjusted_mode->htotal = pixel_clock_hz / (mode->vrefresh * mode->vtotal); > @@ -900,7 +896,11 @@ static void vc4_dsi_encoder_enable(struct drm_encoder *encoder) > vc4_dsi_dump_regs(dsi); > } > > - phy_clock = pixel_clock_hz * dsi->divider; > + /* Round up the clk_set_rate() request slightly, since > + * PLLD_DSI1 is an integer divider and its rate selection will > + * never round up. > + */ > + phy_clock = (pixel_clock_hz + 1000) * dsi->divider; > ret = clk_set_rate(dsi->pll_phy_clock, phy_clock); > if (ret) { > dev_err(&dsi->pdev->dev,