From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752670AbdJMUnK (ORCPT ); Fri, 13 Oct 2017 16:43:10 -0400 Received: from mx1.redhat.com ([209.132.183.28]:3306 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752483AbdJMUnF (ORCPT ); Fri, 13 Oct 2017 16:43:05 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 21EED81E09 Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=rkrcmar@redhat.com Date: Fri, 13 Oct 2017 22:43:02 +0200 From: Radim =?utf-8?B?S3LEjW3DocWZ?= To: Wanpeng Li Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Paolo Bonzini , Wanpeng Li Subject: Re: [PATCH] KVM: LAPIC: Level-sensitive interrupts are not support for LINT1 Message-ID: <20171013204301.GB30745@flask> References: <1507868873-6756-1-git-send-email-wanpeng.li@hotmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1507868873-6756-1-git-send-email-wanpeng.li@hotmail.com> X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.25]); Fri, 13 Oct 2017 20:43:05 +0000 (UTC) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 2017-10-12 21:27-0700, Wanpeng Li: > From: Wanpeng Li > > SDM 10.5.1 mentioned: > Software should always set the trigger mode in the LVT LINT1 register to 0 (edge > sensitive). Level-sensitive interrupts are not supported from LINT1. > > I can intercept both Linux/windows 7/windows 2016 guests on my hand will set > Level-sensitive trigger mode to LVT LINT1 register during boot. And there is no problem with that, software can do that, delivery through LINT1 is just undefined with that (most likely behaviors are: deliver as edge and don't deliver.). > This patch avoids the software too fool to set the level-sensitive trigger mode > to LVT LINT1 register. The software should see the value it writes, though, so the current behavior is better. Do we hit a KVM bug if the software uses APIC_LVT_LEVEL_TRIGGER? Thanks. > Cc: Paolo Bonzini > Cc: Radim Krčmář > Signed-off-by: Wanpeng Li > --- > arch/x86/kvm/lapic.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c > index a778f1a..26593c7 100644 > --- a/arch/x86/kvm/lapic.c > +++ b/arch/x86/kvm/lapic.c > @@ -1758,6 +1758,8 @@ int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) > val |= APIC_LVT_MASKED; > > val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4]; > + if (reg == APIC_LVT1) > + val &= ~APIC_LVT_LEVEL_TRIGGER; > kvm_lapic_set_reg(apic, reg, val); > > break; > -- > 2.7.4 >