Re: [PATCH] perf vendor events arm64: Add hip08 implementation defined PMU core events

Will Deacon
2017-10-18T10:49:10Z

On Wed, Oct 18, 2017 at 10:25:39AM +0100, John Garry wrote:
> On 17/10/2017 13:59, Will Deacon wrote:
> >Hi Shaokun,
> >
> >Thanks for the patch. One comment below.
> >
> >On Tue, Oct 17, 2017 at 03:01:39PM +0800, Shaokun Zhang wrote:
> >>This is a short list of useful implementation defined PMU events of
> >>hip08, other supported events are not listed in this JSON file.
> >>
> >>This patch is dependent on Cavium's patch-v9 (Add support for
> >>ThunderX2 pmu events using json files), Link:
> >>https://www.spinics.net/lists/arm-kernel/msg611895.html
> >>
> >>Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
> >>Cc: Peter Zijlstra <peterz@infradead.org>
> >>Cc: Ingo Molnar <mingo@redhat.com>
> >>Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
> >>Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
> >>Cc: Will Deacon <will.deacon@arm.com>
> >>Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
> >>Cc: John Garry <john.garry@huawei.com>
> >>---
> >> .../arch/arm64/hisilicon/hip08-imp-def.json | 176 +++++++++++++++++++++
> >> tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 +
> >> 2 files changed, 177 insertions(+)
> >> create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip08-imp-def.json
> >>
> >>diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08-imp-def.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08-imp-def.json
> >>new file mode 100644
> >>index 0000000..6bb31da
> >>--- /dev/null
> >>+++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08-imp-def.json
> >>@@ -0,0 +1,176 @@
> >>+[
> >>+ {
> >>+ "PublicDescription": "Attributable Level 1 data cache access, read",
> >>+ "EventCode": "0x40",
> >>+ "EventName": "L1D_CACHE_RD",
> >>+ "BriefDescription": "L1D cache access, read",
> >>+ },
> >>+ {
> >>+ "PublicDescription": "Attributable Level 1 data cache access, write",
> >>+ "EventCode": "0x41",
> >>+ "EventName": "L1D_CACHE_WR",
> >>+ "BriefDescription": "L1D cache access, write",
> >>+ },
> >
> >So these are the same as the events in cavium/thunderx2-imp-def.json and
> >should be factored out. In fact, ARM recommends event numbers for 0x40-0xBF,
> >so the best thing would be to have those defined in their own file, then
> >have a way for the various CPU-specific .json files to pick and chose the
> >events they need from there.
>
> Right, this seems reasonable. Just need to check on feasible.
>
> In terms of coordinating this work, shall we do it? Will arm64+ThunderX
> support be accepted as is?

Yes, that would be my preference if you don't mind.

Will