From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751441AbdJRKtK (ORCPT ); Wed, 18 Oct 2017 06:49:10 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:37582 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750880AbdJRKtG (ORCPT ); Wed, 18 Oct 2017 06:49:06 -0400 Date: Wed, 18 Oct 2017 11:49:11 +0100 From: Will Deacon To: John Garry Cc: Shaokun Zhang , Ganapatrao Kulkarni , linux-kernel@vger.kernel.org, linuxarm@huawei.com, jonathan.cameron@huawei.com, Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Alexander Shishkin Subject: Re: [PATCH] perf vendor events arm64: Add hip08 implementation defined PMU core events Message-ID: <20171018104910.GB11669@arm.com> References: <1508223699-39274-1-git-send-email-zhangshaokun@hisilicon.com> <20171017125926.GE14051@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Oct 18, 2017 at 10:25:39AM +0100, John Garry wrote: > On 17/10/2017 13:59, Will Deacon wrote: > >Hi Shaokun, > > > >Thanks for the patch. One comment below. > > > >On Tue, Oct 17, 2017 at 03:01:39PM +0800, Shaokun Zhang wrote: > >>This is a short list of useful implementation defined PMU events of > >>hip08, other supported events are not listed in this JSON file. > >> > >>This patch is dependent on Cavium's patch-v9 (Add support for > >>ThunderX2 pmu events using json files), Link: > >>https://www.spinics.net/lists/arm-kernel/msg611895.html > >> > >>Signed-off-by: Shaokun Zhang > >>Cc: Peter Zijlstra > >>Cc: Ingo Molnar > >>Cc: Arnaldo Carvalho de Melo > >>Cc: Alexander Shishkin > >>Cc: Will Deacon > >>Cc: Ganapatrao Kulkarni > >>Cc: John Garry > >>--- > >> .../arch/arm64/hisilicon/hip08-imp-def.json | 176 +++++++++++++++++++++ > >> tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 + > >> 2 files changed, 177 insertions(+) > >> create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip08-imp-def.json > >> > >>diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08-imp-def.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08-imp-def.json > >>new file mode 100644 > >>index 0000000..6bb31da > >>--- /dev/null > >>+++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08-imp-def.json > >>@@ -0,0 +1,176 @@ > >>+[ > >>+ { > >>+ "PublicDescription": "Attributable Level 1 data cache access, read", > >>+ "EventCode": "0x40", > >>+ "EventName": "L1D_CACHE_RD", > >>+ "BriefDescription": "L1D cache access, read", > >>+ }, > >>+ { > >>+ "PublicDescription": "Attributable Level 1 data cache access, write", > >>+ "EventCode": "0x41", > >>+ "EventName": "L1D_CACHE_WR", > >>+ "BriefDescription": "L1D cache access, write", > >>+ }, > > > >So these are the same as the events in cavium/thunderx2-imp-def.json and > >should be factored out. In fact, ARM recommends event numbers for 0x40-0xBF, > >so the best thing would be to have those defined in their own file, then > >have a way for the various CPU-specific .json files to pick and chose the > >events they need from there. > > Right, this seems reasonable. Just need to check on feasible. > > In terms of coordinating this work, shall we do it? Will arm64+ThunderX > support be accepted as is? Yes, that would be my preference if you don't mind. Will