* [PATCH] perf vendor events arm64: Add hip08 implementation defined PMU core events
@ 2017-10-17 7:01 Shaokun Zhang
2017-10-17 12:59 ` Will Deacon
0 siblings, 1 reply; 11+ messages in thread
From: Shaokun Zhang @ 2017-10-17 7:01 UTC (permalink / raw)
To: linux-kernel, linuxarm
Cc: jonathan.cameron, Shaokun Zhang, Peter Zijlstra, Ingo Molnar,
Arnaldo Carvalho de Melo, Alexander Shishkin, Will Deacon,
Ganapatrao Kulkarni, John Garry
This is a short list of useful implementation defined PMU events of
hip08, other supported events are not listed in this JSON file.
This patch is dependent on Cavium's patch-v9 (Add support for
ThunderX2 pmu events using json files), Link:
https://www.spinics.net/lists/arm-kernel/msg611895.html
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Cc: John Garry <john.garry@huawei.com>
---
.../arch/arm64/hisilicon/hip08-imp-def.json | 176 +++++++++++++++++++++
tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 +
2 files changed, 177 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip08-imp-def.json
diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08-imp-def.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08-imp-def.json
new file mode 100644
index 0000000..6bb31da
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08-imp-def.json
@@ -0,0 +1,176 @@
+[
+ {
+ "PublicDescription": "Attributable Level 1 data cache access, read",
+ "EventCode": "0x40",
+ "EventName": "L1D_CACHE_RD",
+ "BriefDescription": "L1D cache access, read",
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache access, write",
+ "EventCode": "0x41",
+ "EventName": "L1D_CACHE_WR",
+ "BriefDescription": "L1D cache access, write",
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache refill, read",
+ "EventCode": "0x42",
+ "EventName": "L1D_CACHE_REFILL_RD",
+ "BriefDescription": "L1D cache refill, read",
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache refill, write",
+ "EventCode": "0x43",
+ "EventName": "L1D_CACHE_REFILL_WR",
+ "BriefDescription": "L1D cache refill, write",
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache Write-Back, victim",
+ "EventCode": "0x46",
+ "EventName": "L1D_CACHE_WB_VICTIM",
+ "BriefDescription": "L1D cache Write-Back, victim",
+ },
+ {
+ "PublicDescription": "Level 1 data cache Write-Back, cleaning and coherency",
+ "EventCode": "0x47",
+ "EventName": "L1D_CACHE_WB_CLEAN",
+ "BriefDescription": "L1D cache Write-Back, cleaning and coherency",
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache invalidate",
+ "EventCode": "0x48",
+ "EventName": "L1D_CACHE_INVAL",
+ "BriefDescription": "L1D cache invalidate",
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data TLB refill, read",
+ "EventCode": "0x4C",
+ "EventName": "L1D_TLB_REFILL_RD",
+ "BriefDescription": "L1D tlb refill, read",
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data TLB refill, write",
+ "EventCode": "0x4D",
+ "EventName": "L1D_TLB_REFILL_WR",
+ "BriefDescription": "L1D tlb refill, write",
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data or unified TLB access, read",
+ "EventCode": "0x4E",
+ "EventName": "L1D_TLB_RD",
+ "BriefDescription": "L1D tlb access, read",
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data or unified TLB access, write",
+ "EventCode": "0x4F",
+ "EventName": "L1D_TLB_WR",
+ "BriefDescription": "L1D tlb access, write",
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data cache access, read",
+ "EventCode": "0x50",
+ "EventName": "L2D_CACHE_RD",
+ "BriefDescription": "L2D cache access, read",
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data cache access, write",
+ "EventCode": "0x51",
+ "EventName": "L2D_CACHE_WR",
+ "BriefDescription": "L2D cache access, write",
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data cache refill, read",
+ "EventCode": "0x52",
+ "EventName": "L2D_CACHE_REFILL_RD",
+ "BriefDescription": "L2D cache refill, read",
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data cache refill, write",
+ "EventCode": "0x53",
+ "EventName": "L2D_CACHE_REFILL_WR",
+ "BriefDescription": "L2D cache refill, write",
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data cache Write-Back, victim",
+ "EventCode": "0x56",
+ "EventName": "L2D_CACHE_WB_VICTIM",
+ "BriefDescription": "L2D cache Write-Back, victim",
+ },
+ {
+ "PublicDescription": "Level 2 data cache Write-Back, cleaning and coherency",
+ "EventCode": "0x57",
+ "EventName": "L2D_CACHE_WB_CLEAN",
+ "BriefDescription": "L2D cache Write-Back, cleaning and coherency",
+ },
+ {
+ "PublicDescription": "Attributable Level 2 data cache invalidate",
+ "EventCode": "0x58",
+ "EventName": "L2D_CACHE_INVAL",
+ "BriefDescription": "L2D cache invalidate",
+ },
+ {
+ "PublicDescription": "Level 1 instruction cache prefetch access count",
+ "EventCode": "0x102e",
+ "EventName": "L1I_CACHE_PRF",
+ "BriefDescription": "L1I cache prefetch access count",
+ },
+ {
+ "PublicDescription": "Level 1 instruction cache miss due to prefetch access count",
+ "EventCode": "0x102f",
+ "EventName": "L1I_CACHE_PRF_REFILL",
+ "BriefDescription": "L1I cache miss due to prefetch access count",
+ },
+ {
+ "PublicDescription": "Instruction queue is empty",
+ "EventCode": "0x1043",
+ "EventName": "IQ_IS_EMPTY",
+ "BriefDescription": "Instruction queue is empty",
+ },
+ {
+ "PublicDescription": "Instruction fetch stall cycles",
+ "EventCode": "0x1044",
+ "EventName": "IF_IS_STALL",
+ "BriefDescription": "Instruction fetch stall cycles",
+ },
+ {
+ "PublicDescription": "Instructions can receive, but not send",
+ "EventCode": "0x2014",
+ "EventName": "FETCH_BUBBLE",
+ "BriefDescription": "Instructions can receive, but not send",
+ },
+ {
+ "PublicDescription": "Prefetch request from LSU",
+ "EventCode": "0x6013",
+ "EventName": "PRF_REQ",
+ "BriefDescription": "Prefetch request from LSU",
+ },
+ {
+ "PublicDescription": "Hit on prefetched data",
+ "EventCode": "0x6014",
+ "EventName": "HIT_ON_PRF",
+ "BriefDescription": "Hit on prefetched data",
+ },
+ {
+ "PublicDescription": "Cycles of that the number of issuing micro operations are less than 4",
+ "EventCode": "0x7001",
+ "EventName": "EXE_STALL_CYCLE",
+ "BriefDescription": "Cycles of that the number of issue ups are less than 4",
+ },
+ {
+ "PublicDescription": "No any micro operation is issued and meanwhile any load operation is not resolved",
+ "EventCode": "0x7004",
+ "EventName": "MEM_STALL_ANYLOAD",
+ "BriefDescription": "No any micro operation is issued and meanwhile any load operation is not resolved",
+ },
+ {
+ "PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill",
+ "EventCode": "0x7006",
+ "EventName": "MEM_STALL_L1MISS",
+ "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill",
+ },
+ {
+ "PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache",
+ "EventCode": "0x7007",
+ "EventName": "MEM_STALL_L2MISS",
+ "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache",
+ },
+]
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
index 219d675..c68b2b1 100644
--- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -13,3 +13,4 @@
#
#Family-model,Version,Filename,EventType
0x00000000420f5160,v1,cavium,core
+0x00000000480fd010,v1,hisilicon,core
--
1.9.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH] perf vendor events arm64: Add hip08 implementation defined PMU core events
2017-10-17 7:01 [PATCH] perf vendor events arm64: Add hip08 implementation defined PMU core events Shaokun Zhang
@ 2017-10-17 12:59 ` Will Deacon
2017-10-18 9:25 ` John Garry
0 siblings, 1 reply; 11+ messages in thread
From: Will Deacon @ 2017-10-17 12:59 UTC (permalink / raw)
To: Shaokun Zhang
Cc: linux-kernel, linuxarm, jonathan.cameron, Peter Zijlstra,
Ingo Molnar, Arnaldo Carvalho de Melo, Alexander Shishkin,
Ganapatrao Kulkarni, John Garry
Hi Shaokun,
Thanks for the patch. One comment below.
On Tue, Oct 17, 2017 at 03:01:39PM +0800, Shaokun Zhang wrote:
> This is a short list of useful implementation defined PMU events of
> hip08, other supported events are not listed in this JSON file.
>
> This patch is dependent on Cavium's patch-v9 (Add support for
> ThunderX2 pmu events using json files), Link:
> https://www.spinics.net/lists/arm-kernel/msg611895.html
>
> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
> Cc: Peter Zijlstra <peterz@infradead.org>
> Cc: Ingo Molnar <mingo@redhat.com>
> Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
> Cc: John Garry <john.garry@huawei.com>
> ---
> .../arch/arm64/hisilicon/hip08-imp-def.json | 176 +++++++++++++++++++++
> tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 +
> 2 files changed, 177 insertions(+)
> create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip08-imp-def.json
>
> diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08-imp-def.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08-imp-def.json
> new file mode 100644
> index 0000000..6bb31da
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08-imp-def.json
> @@ -0,0 +1,176 @@
> +[
> + {
> + "PublicDescription": "Attributable Level 1 data cache access, read",
> + "EventCode": "0x40",
> + "EventName": "L1D_CACHE_RD",
> + "BriefDescription": "L1D cache access, read",
> + },
> + {
> + "PublicDescription": "Attributable Level 1 data cache access, write",
> + "EventCode": "0x41",
> + "EventName": "L1D_CACHE_WR",
> + "BriefDescription": "L1D cache access, write",
> + },
So these are the same as the events in cavium/thunderx2-imp-def.json and
should be factored out. In fact, ARM recommends event numbers for 0x40-0xBF,
so the best thing would be to have those defined in their own file, then
have a way for the various CPU-specific .json files to pick and chose the
events they need from there.
Will
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] perf vendor events arm64: Add hip08 implementation defined PMU core events
2017-10-17 12:59 ` Will Deacon
@ 2017-10-18 9:25 ` John Garry
2017-10-18 10:49 ` Will Deacon
0 siblings, 1 reply; 11+ messages in thread
From: John Garry @ 2017-10-18 9:25 UTC (permalink / raw)
To: Will Deacon, Shaokun Zhang, Ganapatrao Kulkarni
Cc: linux-kernel, linuxarm, jonathan.cameron, Peter Zijlstra,
Ingo Molnar, Arnaldo Carvalho de Melo, Alexander Shishkin
On 17/10/2017 13:59, Will Deacon wrote:
> Hi Shaokun,
>
> Thanks for the patch. One comment below.
>
> On Tue, Oct 17, 2017 at 03:01:39PM +0800, Shaokun Zhang wrote:
>> This is a short list of useful implementation defined PMU events of
>> hip08, other supported events are not listed in this JSON file.
>>
>> This patch is dependent on Cavium's patch-v9 (Add support for
>> ThunderX2 pmu events using json files), Link:
>> https://www.spinics.net/lists/arm-kernel/msg611895.html
>>
>> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
>> Cc: Peter Zijlstra <peterz@infradead.org>
>> Cc: Ingo Molnar <mingo@redhat.com>
>> Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
>> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
>> Cc: Will Deacon <will.deacon@arm.com>
>> Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
>> Cc: John Garry <john.garry@huawei.com>
>> ---
>> .../arch/arm64/hisilicon/hip08-imp-def.json | 176 +++++++++++++++++++++
>> tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 +
>> 2 files changed, 177 insertions(+)
>> create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip08-imp-def.json
>>
>> diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08-imp-def.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08-imp-def.json
>> new file mode 100644
>> index 0000000..6bb31da
>> --- /dev/null
>> +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08-imp-def.json
>> @@ -0,0 +1,176 @@
>> +[
>> + {
>> + "PublicDescription": "Attributable Level 1 data cache access, read",
>> + "EventCode": "0x40",
>> + "EventName": "L1D_CACHE_RD",
>> + "BriefDescription": "L1D cache access, read",
>> + },
>> + {
>> + "PublicDescription": "Attributable Level 1 data cache access, write",
>> + "EventCode": "0x41",
>> + "EventName": "L1D_CACHE_WR",
>> + "BriefDescription": "L1D cache access, write",
>> + },
>
> So these are the same as the events in cavium/thunderx2-imp-def.json and
> should be factored out. In fact, ARM recommends event numbers for 0x40-0xBF,
> so the best thing would be to have those defined in their own file, then
> have a way for the various CPU-specific .json files to pick and chose the
> events they need from there.
Right, this seems reasonable. Just need to check on feasible.
In terms of coordinating this work, shall we do it? Will arm64+ThunderX
support be accepted as is?
Thanks,
John
>
> Will
>
> .
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] perf vendor events arm64: Add hip08 implementation defined PMU core events
2017-10-18 9:25 ` John Garry
@ 2017-10-18 10:49 ` Will Deacon
2017-10-18 16:37 ` John Garry
0 siblings, 1 reply; 11+ messages in thread
From: Will Deacon @ 2017-10-18 10:49 UTC (permalink / raw)
To: John Garry
Cc: Shaokun Zhang, Ganapatrao Kulkarni, linux-kernel, linuxarm,
jonathan.cameron, Peter Zijlstra, Ingo Molnar,
Arnaldo Carvalho de Melo, Alexander Shishkin
On Wed, Oct 18, 2017 at 10:25:39AM +0100, John Garry wrote:
> On 17/10/2017 13:59, Will Deacon wrote:
> >Hi Shaokun,
> >
> >Thanks for the patch. One comment below.
> >
> >On Tue, Oct 17, 2017 at 03:01:39PM +0800, Shaokun Zhang wrote:
> >>This is a short list of useful implementation defined PMU events of
> >>hip08, other supported events are not listed in this JSON file.
> >>
> >>This patch is dependent on Cavium's patch-v9 (Add support for
> >>ThunderX2 pmu events using json files), Link:
> >>https://www.spinics.net/lists/arm-kernel/msg611895.html
> >>
> >>Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
> >>Cc: Peter Zijlstra <peterz@infradead.org>
> >>Cc: Ingo Molnar <mingo@redhat.com>
> >>Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
> >>Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
> >>Cc: Will Deacon <will.deacon@arm.com>
> >>Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
> >>Cc: John Garry <john.garry@huawei.com>
> >>---
> >> .../arch/arm64/hisilicon/hip08-imp-def.json | 176 +++++++++++++++++++++
> >> tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 +
> >> 2 files changed, 177 insertions(+)
> >> create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip08-imp-def.json
> >>
> >>diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08-imp-def.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08-imp-def.json
> >>new file mode 100644
> >>index 0000000..6bb31da
> >>--- /dev/null
> >>+++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08-imp-def.json
> >>@@ -0,0 +1,176 @@
> >>+[
> >>+ {
> >>+ "PublicDescription": "Attributable Level 1 data cache access, read",
> >>+ "EventCode": "0x40",
> >>+ "EventName": "L1D_CACHE_RD",
> >>+ "BriefDescription": "L1D cache access, read",
> >>+ },
> >>+ {
> >>+ "PublicDescription": "Attributable Level 1 data cache access, write",
> >>+ "EventCode": "0x41",
> >>+ "EventName": "L1D_CACHE_WR",
> >>+ "BriefDescription": "L1D cache access, write",
> >>+ },
> >
> >So these are the same as the events in cavium/thunderx2-imp-def.json and
> >should be factored out. In fact, ARM recommends event numbers for 0x40-0xBF,
> >so the best thing would be to have those defined in their own file, then
> >have a way for the various CPU-specific .json files to pick and chose the
> >events they need from there.
>
> Right, this seems reasonable. Just need to check on feasible.
>
> In terms of coordinating this work, shall we do it? Will arm64+ThunderX
> support be accepted as is?
Yes, that would be my preference if you don't mind.
Will
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] perf vendor events arm64: Add hip08 implementation defined PMU core events
2017-10-18 10:49 ` Will Deacon
@ 2017-10-18 16:37 ` John Garry
2017-10-18 17:04 ` Will Deacon
2017-10-18 17:20 ` Ganapatrao Kulkarni
0 siblings, 2 replies; 11+ messages in thread
From: John Garry @ 2017-10-18 16:37 UTC (permalink / raw)
To: Will Deacon
Cc: Shaokun Zhang, Ganapatrao Kulkarni, linux-kernel, linuxarm,
jonathan.cameron, Peter Zijlstra, Ingo Molnar,
Arnaldo Carvalho de Melo, Alexander Shishkin
On 18/10/2017 11:49, Will Deacon wrote:
> On Wed, Oct 18, 2017 at 10:25:39AM +0100, John Garry wrote:
>> On 17/10/2017 13:59, Will Deacon wrote:
>>> Hi Shaokun,
>>>
>>> Thanks for the patch. One comment below.
>>>
>>> On Tue, Oct 17, 2017 at 03:01:39PM +0800, Shaokun Zhang wrote:
>>>> This is a short list of useful implementation defined PMU events of
>>>> hip08, other supported events are not listed in this JSON file.
>>>>
>>>> This patch is dependent on Cavium's patch-v9 (Add support for
>>>> ThunderX2 pmu events using json files), Link:
>>>> https://www.spinics.net/lists/arm-kernel/msg611895.html
>>>>
>>>> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
>>>> Cc: Peter Zijlstra <peterz@infradead.org>
>>>> Cc: Ingo Molnar <mingo@redhat.com>
>>>> Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
>>>> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
>>>> Cc: Will Deacon <will.deacon@arm.com>
>>>> Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
>>>> Cc: John Garry <john.garry@huawei.com>
>>>> ---
>>>> .../arch/arm64/hisilicon/hip08-imp-def.json | 176 +++++++++++++++++++++
>>>> tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 +
>>>> 2 files changed, 177 insertions(+)
>>>> create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip08-imp-def.json
>>>>
>>>> diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08-imp-def.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08-imp-def.json
>>>> new file mode 100644
>>>> index 0000000..6bb31da
>>>> --- /dev/null
>>>> +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08-imp-def.json
>>>> @@ -0,0 +1,176 @@
>>>> +[
>>>> + {
>>>> + "PublicDescription": "Attributable Level 1 data cache access, read",
>>>> + "EventCode": "0x40",
>>>> + "EventName": "L1D_CACHE_RD",
>>>> + "BriefDescription": "L1D cache access, read",
>>>> + },
>>>> + {
>>>> + "PublicDescription": "Attributable Level 1 data cache access, write",
>>>> + "EventCode": "0x41",
>>>> + "EventName": "L1D_CACHE_WR",
>>>> + "BriefDescription": "L1D cache access, write",
>>>> + },
>>>
>>> So these are the same as the events in cavium/thunderx2-imp-def.json and
>>> should be factored out. In fact, ARM recommends event numbers for 0x40-0xBF,
>>> so the best thing would be to have those defined in their own file, then
>>> have a way for the various CPU-specific .json files to pick and chose the
>>> events they need from there.
>>
>> Right, this seems reasonable. Just need to check on feasible.
>>
>> In terms of coordinating this work, shall we do it? Will arm64+ThunderX
>> support be accepted as is?
>
> Yes, that would be my preference if you don't mind.
Cool.
I am looking at this topic now. But I am doubting the folder structure
again.
Firstly, we still have this comment in the README:
All the topic JSON files for a CPU model/family should be in a separate
sub directory.
Now, when thunderx3 or hip09 comes along, I assume that their jsons will
similarly go into cavium and hisilcon folders, respectively. So, for
example, we add thunderx3 json, like this:
arm64/cavium/thunderx3-imp-def.json
[
{
"PublicDescription": "foo",
"EventCode": "0x40",
"EventName": "bar",
"BriefDescription": "sieve",
},
]
#Family-model,Version,Filename,EventType
0x00000000420f5160,v1,cavium,core
0x00000000420f5161,v1,cavium,core
Then we have generated pmu_events.c, like this:
#include "../../pmu-events/pmu-events.h"
struct pmu_event pme_cavium[] = {
{
.name = "bar",
.event = "event=0x40",
.desc = "sieve",
.topic = "thunderx3 imp def",
.long_desc = "foo",
},
{
.name = "l1d_cache_rd",
.event = "event=0x40",
.desc = "L1D cache read",
.topic = "thunderx2 imp def",
.long_desc = "Attributable Level 1 data cache access, read",
},
{
.name = "l1d_cache_wr",
.event = "event=0x41",
.desc = "L1D cache write",
.topic = "thunderx2 imp def",
.long_desc = "Attributable Level 1 data cache access, write ",
},
[ ... ]
{
.name = 0,
.event = 0,
.desc = 0,
},
};
struct pmu_events_map pmu_events_map[] = {
{
.cpuid = "0x00000000420f5160",
.version = "v1",
.type = "core",
.table = pme_cavium
},
{
.cpuid = "0x00000000420f5161",
.version = "v1",
.type = "core",
.table = pme_cavium
},
{
.cpuid = 0,
.version = 0,
.type = 0,
.table = 0,
},
};
It doesn't look right, espcially since we have conflicting definitions
for event 0x40. We really should have table per cpu.
John
>
> Will
>
> .
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] perf vendor events arm64: Add hip08 implementation defined PMU core events
2017-10-18 16:37 ` John Garry
@ 2017-10-18 17:04 ` Will Deacon
2017-10-19 9:20 ` John Garry
2017-10-18 17:20 ` Ganapatrao Kulkarni
1 sibling, 1 reply; 11+ messages in thread
From: Will Deacon @ 2017-10-18 17:04 UTC (permalink / raw)
To: John Garry
Cc: Shaokun Zhang, Ganapatrao Kulkarni, linux-kernel, linuxarm,
jonathan.cameron, Peter Zijlstra, Ingo Molnar,
Arnaldo Carvalho de Melo, Alexander Shishkin
Hi John,
On Wed, Oct 18, 2017 at 05:37:03PM +0100, John Garry wrote:
> On 18/10/2017 11:49, Will Deacon wrote:
> >On Wed, Oct 18, 2017 at 10:25:39AM +0100, John Garry wrote:
> >>On 17/10/2017 13:59, Will Deacon wrote:
> >>>On Tue, Oct 17, 2017 at 03:01:39PM +0800, Shaokun Zhang wrote:
> >>>>diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08-imp-def.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08-imp-def.json
> >>>>new file mode 100644
> >>>>index 0000000..6bb31da
> >>>>--- /dev/null
> >>>>+++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08-imp-def.json
> >>>>@@ -0,0 +1,176 @@
> >>>>+[
> >>>>+ {
> >>>>+ "PublicDescription": "Attributable Level 1 data cache access, read",
> >>>>+ "EventCode": "0x40",
> >>>>+ "EventName": "L1D_CACHE_RD",
> >>>>+ "BriefDescription": "L1D cache access, read",
> >>>>+ },
> >>>>+ {
> >>>>+ "PublicDescription": "Attributable Level 1 data cache access, write",
> >>>>+ "EventCode": "0x41",
> >>>>+ "EventName": "L1D_CACHE_WR",
> >>>>+ "BriefDescription": "L1D cache access, write",
> >>>>+ },
> >>>
> >>>So these are the same as the events in cavium/thunderx2-imp-def.json and
> >>>should be factored out. In fact, ARM recommends event numbers for 0x40-0xBF,
> >>>so the best thing would be to have those defined in their own file, then
> >>>have a way for the various CPU-specific .json files to pick and chose the
> >>>events they need from there.
> >>
> >>Right, this seems reasonable. Just need to check on feasible.
> >>
> >>In terms of coordinating this work, shall we do it? Will arm64+ThunderX
> >>support be accepted as is?
> >
> >Yes, that would be my preference if you don't mind.
>
>
> Cool.
>
> I am looking at this topic now. But I am doubting the folder structure
> again.
>
> Firstly, we still have this comment in the README:
> All the topic JSON files for a CPU model/family should be in a separate
> sub directory.
>
> Now, when thunderx3 or hip09 comes along, I assume that their jsons will
> similarly go into cavium and hisilcon folders, respectively. So, for
> example, we add thunderx3 json, like this:
> arm64/cavium/thunderx3-imp-def.json
> [
> {
> "PublicDescription": "foo",
> "EventCode": "0x40",
> "EventName": "bar",
> "BriefDescription": "sieve",
> },
> ]
Hang on, event 0x40 is one of the common ones, so that should be somewhere
else like arm64/armv8-common.json.
> #Family-model,Version,Filename,EventType
> 0x00000000420f5160,v1,cavium,core
> 0x00000000420f5161,v1,cavium,core
>
> Then we have generated pmu_events.c, like this:
> #include "../../pmu-events/pmu-events.h"
> struct pmu_event pme_cavium[] = {
> {
> .name = "bar",
> .event = "event=0x40",
> .desc = "sieve",
> .topic = "thunderx3 imp def",
> .long_desc = "foo",
> },
> {
> .name = "l1d_cache_rd",
> .event = "event=0x40",
> .desc = "L1D cache read",
> .topic = "thunderx2 imp def",
> .long_desc = "Attributable Level 1 data cache access, read",
> },
> {
> .name = "l1d_cache_wr",
> .event = "event=0x41",
> .desc = "L1D cache write",
> .topic = "thunderx2 imp def",
> .long_desc = "Attributable Level 1 data cache access, write ",
> },
>
> [ ... ]
>
> {
> .name = 0,
> .event = 0,
> .desc = 0,
> },
> };
> struct pmu_events_map pmu_events_map[] = {
> {
> .cpuid = "0x00000000420f5160",
> .version = "v1",
> .type = "core",
> .table = pme_cavium
> },
> {
> .cpuid = "0x00000000420f5161",
> .version = "v1",
> .type = "core",
> .table = pme_cavium
> },
> {
> .cpuid = 0,
> .version = 0,
> .type = 0,
> .table = 0,
> },
> };
>
> It doesn't look right, espcially since we have conflicting definitions for
> event 0x40. We really should have table per cpu.
There should be one definition of event 0x40 and it should use the wording
from the ARM ARM:
0x0040 , L1D_CACHE_RD, Attributable Level 1 data cache access, read
This event is similar to Level 1 data cache access, L1D_CACHE,
but the counter counts only memory-read operations that access
at least the Level 1 data or unified cache.
I think that the tricky bit is working out which subset of the
armv8-common.json file applies to a given CPU, but I was hoping you'd have
some ideas about that, even if it's an additional build step when building
perf to generate the final JSON files
Will
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] perf vendor events arm64: Add hip08 implementation defined PMU core events
2017-10-18 16:37 ` John Garry
2017-10-18 17:04 ` Will Deacon
@ 2017-10-18 17:20 ` Ganapatrao Kulkarni
2017-10-19 10:29 ` John Garry
1 sibling, 1 reply; 11+ messages in thread
From: Ganapatrao Kulkarni @ 2017-10-18 17:20 UTC (permalink / raw)
To: John Garry
Cc: Will Deacon, Shaokun Zhang, Ganapatrao Kulkarni, linux-kernel,
Linuxarm, jonathan.cameron, Peter Zijlstra, Ingo Molnar,
Arnaldo Carvalho de Melo, Alexander Shishkin
Hi John,
On Wed, Oct 18, 2017 at 10:07 PM, John Garry <john.garry@huawei.com> wrote:
> On 18/10/2017 11:49, Will Deacon wrote:
>>
>> On Wed, Oct 18, 2017 at 10:25:39AM +0100, John Garry wrote:
>>>
>>> On 17/10/2017 13:59, Will Deacon wrote:
>>>>
>>>> Hi Shaokun,
>>>>
>>>> Thanks for the patch. One comment below.
>>>>
>>>> On Tue, Oct 17, 2017 at 03:01:39PM +0800, Shaokun Zhang wrote:
>>>>>
>>>>> This is a short list of useful implementation defined PMU events of
>>>>> hip08, other supported events are not listed in this JSON file.
>>>>>
>>>>> This patch is dependent on Cavium's patch-v9 (Add support for
>>>>> ThunderX2 pmu events using json files), Link:
>>>>> https://www.spinics.net/lists/arm-kernel/msg611895.html
>>>>>
>>>>> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
>>>>> Cc: Peter Zijlstra <peterz@infradead.org>
>>>>> Cc: Ingo Molnar <mingo@redhat.com>
>>>>> Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
>>>>> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
>>>>> Cc: Will Deacon <will.deacon@arm.com>
>>>>> Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
>>>>> Cc: John Garry <john.garry@huawei.com>
>>>>> ---
>>>>> .../arch/arm64/hisilicon/hip08-imp-def.json | 176
>>>>> +++++++++++++++++++++
>>>>> tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 +
>>>>> 2 files changed, 177 insertions(+)
>>>>> create mode 100644
>>>>> tools/perf/pmu-events/arch/arm64/hisilicon/hip08-imp-def.json
>>>>>
>>>>> diff --git
>>>>> a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08-imp-def.json
>>>>> b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08-imp-def.json
>>>>> new file mode 100644
>>>>> index 0000000..6bb31da
>>>>> --- /dev/null
>>>>> +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08-imp-def.json
>>>>> @@ -0,0 +1,176 @@
>>>>> +[
>>>>> + {
>>>>> + "PublicDescription": "Attributable Level 1 data cache access,
>>>>> read",
>>>>> + "EventCode": "0x40",
>>>>> + "EventName": "L1D_CACHE_RD",
>>>>> + "BriefDescription": "L1D cache access, read",
>>>>> + },
>>>>> + {
>>>>> + "PublicDescription": "Attributable Level 1 data cache access,
>>>>> write",
>>>>> + "EventCode": "0x41",
>>>>> + "EventName": "L1D_CACHE_WR",
>>>>> + "BriefDescription": "L1D cache access, write",
>>>>> + },
>>>>
>>>>
>>>> So these are the same as the events in cavium/thunderx2-imp-def.json and
>>>> should be factored out. In fact, ARM recommends event numbers for
>>>> 0x40-0xBF,
>>>> so the best thing would be to have those defined in their own file, then
>>>> have a way for the various CPU-specific .json files to pick and chose
>>>> the
>>>> events they need from there.
>>>
>>>
>>> Right, this seems reasonable. Just need to check on feasible.
>>>
>>> In terms of coordinating this work, shall we do it? Will arm64+ThunderX
>>> support be accepted as is?
>>
>>
>> Yes, that would be my preference if you don't mind.
>
>
>
> Cool.
>
> I am looking at this topic now. But I am doubting the folder structure
> again.
>
> Firstly, we still have this comment in the README:
> All the topic JSON files for a CPU model/family should be in a separate
> sub directory.
>
> Now, when thunderx3 or hip09 comes along, I assume that their jsons will
> similarly go into cavium and hisilcon folders, respectively. So, for
> example, we add thunderx3 json, like this:
> arm64/cavium/thunderx3-imp-def.json
> [
> {
> "PublicDescription": "foo",
> "EventCode": "0x40",
> "EventName": "bar",
> "BriefDescription": "sieve",
> },
> ]
>
> #Family-model,Version,Filename,EventType
> 0x00000000420f5160,v1,cavium,core
> 0x00000000420f5161,v1,cavium,core
certainly, there is Part number(PartNum, bits [15:4] ) change from
thunderx2 to thunderx3.
thunderx3 should have its own json file describing all its supported events.
same applies to other SoCs as well.
IIUC, the idea of ignoring Revision and Variants is that, the PMU
design/version wont change across Revisions and Variants.
>
> Then we have generated pmu_events.c, like this:
> #include "../../pmu-events/pmu-events.h"
> struct pmu_event pme_cavium[] = {
> {
> .name = "bar",
> .event = "event=0x40",
> .desc = "sieve",
> .topic = "thunderx3 imp def",
> .long_desc = "foo",
> },
> {
> .name = "l1d_cache_rd",
> .event = "event=0x40",
> .desc = "L1D cache read",
> .topic = "thunderx2 imp def",
> .long_desc = "Attributable Level 1 data cache access, read",
> },
> {
> .name = "l1d_cache_wr",
> .event = "event=0x41",
> .desc = "L1D cache write",
> .topic = "thunderx2 imp def",
> .long_desc = "Attributable Level 1 data cache access, write ",
> },
>
> [ ... ]
>
> {
> .name = 0,
> .event = 0,
> .desc = 0,
> },
> };
> struct pmu_events_map pmu_events_map[] = {
> {
> .cpuid = "0x00000000420f5160",
> .version = "v1",
> .type = "core",
> .table = pme_cavium
> },
> {
> .cpuid = "0x00000000420f5161",
> .version = "v1",
> .type = "core",
> .table = pme_cavium
> },
> {
> .cpuid = 0,
> .version = 0,
> .type = 0,
> .table = 0,
> },
> };
>
> It doesn't look right, espcially since we have conflicting definitions for
> event 0x40. We really should have table per cpu.
as i said above, there is no possibility of having different events
mapped to same event id on a given platform.
>
> John
>
>
>>
>> Will
>>
>> .
>>
>
>
thanks
Ganapat
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] perf vendor events arm64: Add hip08 implementation defined PMU core events
2017-10-18 17:04 ` Will Deacon
@ 2017-10-19 9:20 ` John Garry
0 siblings, 0 replies; 11+ messages in thread
From: John Garry @ 2017-10-19 9:20 UTC (permalink / raw)
To: Will Deacon
Cc: Shaokun Zhang, Ganapatrao Kulkarni, linux-kernel, linuxarm,
jonathan.cameron, Peter Zijlstra, Ingo Molnar,
Arnaldo Carvalho de Melo, Alexander Shishkin
>> I am looking at this topic now. But I am doubting the folder structure
>> again.
>>
>> Firstly, we still have this comment in the README:
>> All the topic JSON files for a CPU model/family should be in a separate
>> sub directory.
>>
>> Now, when thunderx3 or hip09 comes along, I assume that their jsons will
>> similarly go into cavium and hisilcon folders, respectively. So, for
>> example, we add thunderx3 json, like this:
>> arm64/cavium/thunderx3-imp-def.json
>> [
>> {
>> "PublicDescription": "foo",
>> "EventCode": "0x40",
>> "EventName": "bar",
>> "BriefDescription": "sieve",
>> },
>> ]
>
> Hang on, event 0x40 is one of the common ones, so that should be somewhere
> else like arm64/armv8-common.json.
Hi Will,
The example I gave was poor, especially since 0x40 is one the events I
am trying to commonise and it is also a recommended event.
It's the IMPLEMENTATION DEFINED events which I am worried about, which
ThunderX2 does not seem to have.
Ok, as another example, consider this possibility of hip08 and hip09 not
have the same event mappings for all IMPLEMENTATION DEFINED events, like
this:
hip08 json:
[
{
"PublicDescription": "Attributable Level 1 data cache access,
read",
"EventCode": "0x40",
"EventName": "L1D_CACHE_RD",
"BriefDescription": "L1D cache access, read",
},
[...]
{
"PublicDescription": "Cycles of that the number of issuing
micro operations are less than 4",
"EventCode": "0x7001",
"EventName": "EXE_STALL_CYCLE",
"BriefDescription": "Cycles of that the number of issue ups are
less than 4",
},
[...]
]
hip09 json is same as hip08, but IMPLEMENTATION DEFINED event 0x7001 has
a different meaning:
{
"PublicDescription": "foo",
"EventCode": "0x7001",
"EventName": "bar",
"BriefDescription": "sieve",
},
So pmu_event.c looks like this:
#include "../../pmu-events/pmu-events.h"
struct pmu_event pme_cavium[] = {
{
.name = "l1d_cache_rd",
.event = "event=0x40",
.desc = "L1D cache read",
.topic = "thunderx2 imp def",
.long_desc = "Attributable Level 1 data cache access, read",
},
[ ... ]
{
.name = 0,
.event = 0,
.desc = 0,
},
};
struct pmu_event pme_hisilicon[] = {
{
.name = "l1d_cache_rd",
.event = "event=0x40",
.desc = "L1D cache access, read",
.topic = "hip08 imp def",
.long_desc = "Attributable Level 1 data cache access, read",
},
{
.name = "l1d_cache_wr",
.event = "event=0x41",
.desc = "L1D cache access, write",
.topic = "hip08 imp def",
.long_desc = "Attributable Level 1 data cache access, write",
},
[ ... ]
{
.name = "hit_on_prf",
.event = "event=0x6014",
.desc = "Hit on prefetched data",
.topic = "hip08 imp def",
.long_desc = "Hit on prefetched data",
},
{
.name = "exe_stall_cycle",
.event = "event=0x7001",
.desc = "Cycles of that the number of issue ups are less than 4",
.topic = "hip08 imp def",
.long_desc = "Cycles of that the number of issuing micro operations
are less than 4",
},
[ ... ]
{
.name = "l1d_cache_rd",
.event = "event=0x40",
.desc = "L1D cache access, read",
.topic = "hip09 imp def",
.long_desc = "Attributable Level 1 data cache access, read",
},
[ ... ]
{
.name = "bar",
.event = "event=0x7001",
.desc = "sieve",
.topic = "hip09 imp def",
.long_desc = "foo",
},
[ ... ]
{
.name = 0,
.event = 0,
.desc = 0,
},
};
struct pmu_events_map pmu_events_map[] = {
{
.cpuid = "0x00000000420f5160",
.version = "v1",
.type = "core",
.table = pme_cavium
},
{
.cpuid = "0x00000000480fd010",
.version = "v1",
.type = "core",
.table = pme_hisilicon
},
{
.cpuid = "0x00000000480fd011",
.version = "v1",
.type = "core",
.table = pme_hisilicon
},
{
.cpuid = 0,
.version = 0,
.type = 0,
.table = 0,
},
};
So you can see conflicting entries for event 0x7001 in pme_hisilicon.
Note: cpuid is not valid, but just shown to be different to illustrate.
>
>> #Family-model,Version,Filename,EventType
>> 0x00000000420f5160,v1,cavium,core
>> 0x00000000420f5161,v1,cavium,core
>>
>> Then we have generated pmu_events.c, like this:
>> #include "../../pmu-events/pmu-events.h"
>> struct pmu_event pme_cavium[] = {
>> {
>> .name = "bar",
>> .event = "event=0x40",
>> .desc = "sieve",
>> .topic = "thunderx3 imp def",
>> .long_desc = "foo",
>> },
>> {
>> .name = "l1d_cache_rd",
>> .event = "event=0x40",
>> .desc = "L1D cache read",
>> .topic = "thunderx2 imp def",
>> .long_desc = "Attributable Level 1 data cache access, read",
>> },
>> {
>> .name = "l1d_cache_wr",
>> .event = "event=0x41",
>> .desc = "L1D cache write",
>> .topic = "thunderx2 imp def",
>> .long_desc = "Attributable Level 1 data cache access, write ",
>> },
>>
>> [ ... ]
>>
>> {
>> .name = 0,
>> .event = 0,
>> .desc = 0,
>> },
>> };
>> struct pmu_events_map pmu_events_map[] = {
>> {
>> .cpuid = "0x00000000420f5160",
>> .version = "v1",
>> .type = "core",
>> .table = pme_cavium
>> },
>> {
>> .cpuid = "0x00000000420f5161",
>> .version = "v1",
>> .type = "core",
>> .table = pme_cavium
>> },
>> {
>> .cpuid = 0,
>> .version = 0,
>> .type = 0,
>> .table = 0,
>> },
>> };
>>
>> It doesn't look right, espcially since we have conflicting definitions for
>> event 0x40. We really should have table per cpu.
>
> There should be one definition of event 0x40 and it should use the wording
> from the ARM ARM:
>
> 0x0040 , L1D_CACHE_RD, Attributable Level 1 data cache access, read
> This event is similar to Level 1 data cache access, L1D_CACHE,
> but the counter counts only memory-read operations that access
> at least the Level 1 data or unified cache.
>
> I think that the tricky bit is working out which subset of the
> armv8-common.json file applies to a given CPU, but I was hoping you'd have
> some ideas about that, even if it's an additional build step when building
> perf to generate the final JSON files
I was looking at this, but I want to be happy with the current solution
before I proceed.
Cheers,
John
>
> Will
>
> .
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] perf vendor events arm64: Add hip08 implementation defined PMU core events
2017-10-18 17:20 ` Ganapatrao Kulkarni
@ 2017-10-19 10:29 ` John Garry
2017-10-25 10:06 ` Ganapatrao Kulkarni
0 siblings, 1 reply; 11+ messages in thread
From: John Garry @ 2017-10-19 10:29 UTC (permalink / raw)
To: Ganapatrao Kulkarni
Cc: Will Deacon, Shaokun Zhang, Ganapatrao Kulkarni, linux-kernel,
Linuxarm, jonathan.cameron, Peter Zijlstra, Ingo Molnar,
Arnaldo Carvalho de Melo, Alexander Shishkin
>>
>> #Family-model,Version,Filename,EventType
>> 0x00000000420f5160,v1,cavium,core
>> 0x00000000420f5161,v1,cavium,core
>
> certainly, there is Part number(PartNum, bits [15:4] ) change from
> thunderx2 to thunderx3.
> thunderx3 should have its own json file describing all its supported events.
> same applies to other SoCs as well.
>
> IIUC, the idea of ignoring Revision and Variants is that, the PMU
> design/version wont change across Revisions and Variants.
>
Hi Ganapatrao,
Right, I should have modified the part num for my illustration, but I am
still concerned. Please see my example in the other mail and check what
I am missing.
Thanks,
John
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] perf vendor events arm64: Add hip08 implementation defined PMU core events
2017-10-19 10:29 ` John Garry
@ 2017-10-25 10:06 ` Ganapatrao Kulkarni
2017-10-25 11:07 ` John Garry
0 siblings, 1 reply; 11+ messages in thread
From: Ganapatrao Kulkarni @ 2017-10-25 10:06 UTC (permalink / raw)
To: John Garry
Cc: Will Deacon, Shaokun Zhang, Ganapatrao Kulkarni, linux-kernel,
Linuxarm, jonathan.cameron, Peter Zijlstra, Ingo Molnar,
Arnaldo Carvalho de Melo, Alexander Shishkin
Hi John,
On Thu, Oct 19, 2017 at 3:59 PM, John Garry <john.garry@huawei.com> wrote:
>>>
>>> #Family-model,Version,Filename,EventType
>>> 0x00000000420f5160,v1,cavium,core
>>> 0x00000000420f5161,v1,cavium,core
>>
>>
>> certainly, there is Part number(PartNum, bits [15:4] ) change from
>> thunderx2 to thunderx3.
>> thunderx3 should have its own json file describing all its supported
>> events.
>> same applies to other SoCs as well.
>>
>> IIUC, the idea of ignoring Revision and Variants is that, the PMU
>> design/version wont change across Revisions and Variants.
>>
>
> Hi Ganapatrao,
>
> Right, I should have modified the part num for my illustration, but I am
> still concerned. Please see my example in the other mail and check what I am
> missing.
ok, then my original naming was more appropriate.
i.e have josn files defined in SoC directory, instead of having single
vendor directory for all SoC json files.
like,
pmu-events/arch/arm64/thunderx2
pmu-events/arch/arm64/thunderx3
pmu-events/arch/arm64/hip08
pmu-events/arch/arm64/hip09
>
> Thanks,
> John
>
>
>
>
thanks
Ganapat
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] perf vendor events arm64: Add hip08 implementation defined PMU core events
2017-10-25 10:06 ` Ganapatrao Kulkarni
@ 2017-10-25 11:07 ` John Garry
0 siblings, 0 replies; 11+ messages in thread
From: John Garry @ 2017-10-25 11:07 UTC (permalink / raw)
To: Ganapatrao Kulkarni
Cc: Will Deacon, Shaokun Zhang, Ganapatrao Kulkarni, linux-kernel,
Linuxarm, jonathan.cameron, Peter Zijlstra, Ingo Molnar,
Arnaldo Carvalho de Melo, Alexander Shishkin
On 25/10/2017 11:06, Ganapatrao Kulkarni wrote:
> Hi John,
>
> On Thu, Oct 19, 2017 at 3:59 PM, John Garry <john.garry@huawei.com> wrote:
>>>>
>>>> #Family-model,Version,Filename,EventType
>>>> 0x00000000420f5160,v1,cavium,core
>>>> 0x00000000420f5161,v1,cavium,core
>>>
>>>
>>> certainly, there is Part number(PartNum, bits [15:4] ) change from
>>> thunderx2 to thunderx3.
>>> thunderx3 should have its own json file describing all its supported
>>> events.
>>> same applies to other SoCs as well.
>>>
>>> IIUC, the idea of ignoring Revision and Variants is that, the PMU
>>> design/version wont change across Revisions and Variants.
>>>
>>
>> Hi Ganapatrao,
>>
>> Right, I should have modified the part num for my illustration, but I am
>> still concerned. Please see my example in the other mail and check what I am
>> missing.
>
Hi Ganapatrao,
> ok, then my original naming was more appropriate.
It was better.
For now, until we introduce > 1 json per vendor, we're fine with the
structure as-is.
> i.e have josn files defined in SoC directory, instead of having single
> vendor directory for all SoC json files.
>
> like,
> pmu-events/arch/arm64/thunderx2
> pmu-events/arch/arm64/thunderx3
> pmu-events/arch/arm64/hip08
> pmu-events/arch/arm64/hip09
We're now looking (slowly) at the task of factoring out the common,
ARM-recommended events, and this directory structure issue is not a
blocker, but clarification would be nice.
Cheers,
John
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2017-10-25 11:08 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-10-17 7:01 [PATCH] perf vendor events arm64: Add hip08 implementation defined PMU core events Shaokun Zhang
2017-10-17 12:59 ` Will Deacon
2017-10-18 9:25 ` John Garry
2017-10-18 10:49 ` Will Deacon
2017-10-18 16:37 ` John Garry
2017-10-18 17:04 ` Will Deacon
2017-10-19 9:20 ` John Garry
2017-10-18 17:20 ` Ganapatrao Kulkarni
2017-10-19 10:29 ` John Garry
2017-10-25 10:06 ` Ganapatrao Kulkarni
2017-10-25 11:07 ` John Garry
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