From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752420AbdJSTZ1 (ORCPT ); Thu, 19 Oct 2017 15:25:27 -0400 Received: from mail-out.m-online.net ([212.18.0.9]:54599 "EHLO mail-out.m-online.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751585AbdJSTZZ (ORCPT ); Thu, 19 Oct 2017 15:25:25 -0400 X-Auth-Info: DD3PChnIRVGhFtDFmT4G3G7pqRlx3sAfR8bal/ndyQA= Date: Thu, 19 Oct 2017 21:25:14 +0200 From: Lukasz Majewski To: Thierry Reding Cc: David Airlie , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] panel: display: Add support for Mitsubishi aa070mc01 TFT panel Message-ID: <20171019212514.5dd45f8a@jawa> In-Reply-To: <20171019081510.GA4459@ulmo> References: <1504863782-3293-1-git-send-email-lukma@denx.de> <20171019081510.GA4459@ulmo> Organization: denx.de X-Mailer: Claws Mail 3.11.1 (GTK+ 2.24.25; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; boundary="Sig_/q0SgOavL/LlbiFeCl_f+M=J"; protocol="application/pgp-signature" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --Sig_/q0SgOavL/LlbiFeCl_f+M=J Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable HI Thierry, > On Fri, Sep 08, 2017 at 11:43:02AM +0200, Lukasz Majewski wrote: > > This commit adds support for Mitsubishi aa070mc01 TFT panel working > > with 8 bit ISP mode (pin 19 "mode" HIGH for 20 pin TFT connector). > >=20 > > Signed-off-by: Lukasz Majewski > > --- > > drivers/gpu/drm/panel/panel-simple.c | 35 > > +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) >=20 > This is missing a device tree binding. >=20 > > diff --git a/drivers/gpu/drm/panel/panel-simple.c > > b/drivers/gpu/drm/panel/panel-simple.c index 3d2cb8b..0c64ec6 100644 > > --- a/drivers/gpu/drm/panel/panel-simple.c > > +++ b/drivers/gpu/drm/panel/panel-simple.c > > @@ -1141,6 +1141,38 @@ static const struct panel_desc > > innolux_g121x1_l03 =3D { }, > > }; > > =20 > > +static const struct drm_display_mode mitsubishi_aa070mc01_mode =3D { > > + .clock =3D 30400, > > + .hdisplay =3D 800, > > + .hsync_start =3D 800 + 0, > > + .hsync_end =3D 800 + 1, > > + .htotal =3D 800 + 0 + 1 + 160, > > + .vdisplay =3D 480, > > + .vsync_start =3D 480 + 0, > > + .vsync_end =3D 480 + 48 + 1, > > + .vtotal =3D 480 + 48 + 1 + 0, > > + .vrefresh =3D 60, > > + .flags =3D DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, > > +}; > > + > > +static const struct panel_desc mitsubishi_aa070mc01 =3D { > > + .modes =3D &mitsubishi_aa070mc01_mode, > > + .num_modes =3D 1, > > + .bpc =3D 8, > > + .size =3D { > > + .width =3D 152, > > + .height =3D 91, > > + }, > > + > > + .delay =3D { > > + .enable =3D 200, > > + .unprepare =3D 200, > > + .disable =3D 400, > > + }, > > + .bus_format =3D MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, > > + .bus_flags =3D DRM_BUS_FLAG_DE_HIGH, > > +}; >=20 > And this isn't sorted properly. >=20 > > + > > static const struct drm_display_mode innolux_n116bge_mode =3D { > > .clock =3D 76420, > > .hdisplay =3D 1366, > > @@ -2029,6 +2061,9 @@ static const struct of_device_id > > platform_of_match[] =3D { .compatible =3D "innolux,g121x1-l03", > > .data =3D &innolux_g121x1_l03, > > }, { > > + .compatible =3D "mitsubishi,aa070mc01-ca1", > > + .data =3D &mitsubishi_aa070mc01, > > + }, { >=20 > Same here. >=20 > Thierry I will prepare ./Documentation/device-tree description for this patch and sort those entries. Thanks for your comments :-) Best regards, Lukasz Majewski -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de --Sig_/q0SgOavL/LlbiFeCl_f+M=J Content-Type: application/pgp-signature Content-Description: OpenPGP digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iEYEARECAAYFAlno/CEACgkQf9/hG2YwgjFnxwCdEmUX2LvlJoxiRcAZSV8odZ76 nGcAnjH+sEfBzicZP7bm6yTirHzIfxgo =a1gG -----END PGP SIGNATURE----- --Sig_/q0SgOavL/LlbiFeCl_f+M=J--