From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752583AbdJTJtd (ORCPT ); Fri, 20 Oct 2017 05:49:33 -0400 Received: from mail-pf0-f193.google.com ([209.85.192.193]:45704 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751878AbdJTJta (ORCPT ); Fri, 20 Oct 2017 05:49:30 -0400 X-Google-Smtp-Source: ABhQp+Toijw7DeXYgEnDrT9G1L03VHP5Uon7lib9ejMKFsZQiR+8Kxh3BtHuQZHPe7jF0QsrxhhJUA== Date: Fri, 20 Oct 2017 02:49:13 -0700 From: Minchan Kim To: Ingo Molnar Cc: "Kirill A. Shutemov" , Ingo Molnar , "Kirill A. Shutemov" , Linus Torvalds , x86@kernel.org, Thomas Gleixner , "H. Peter Anvin" , Andrew Morton , Andy Lutomirski , Cyrill Gorcunov , Borislav Petkov , linux-mm@kvack.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 0/6] Boot-time switching between 4- and 5-level paging for 4.15, Part 1 Message-ID: <20171020094913.GA5359@bgram> References: <20170929140821.37654-1-kirill.shutemov@linux.intel.com> <20171003082754.no6ym45oirah53zp@node.shutemov.name> <20171017154241.f4zaxakfl7fcrdz5@node.shutemov.name> <20171020081853.lmnvaiydxhy5c63t@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20171020081853.lmnvaiydxhy5c63t@gmail.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Ingo, On Fri, Oct 20, 2017 at 10:18:53AM +0200, Ingo Molnar wrote: > > * Kirill A. Shutemov wrote: > > > On Tue, Oct 03, 2017 at 11:27:54AM +0300, Kirill A. Shutemov wrote: > > > On Fri, Sep 29, 2017 at 05:08:15PM +0300, Kirill A. Shutemov wrote: > > > > The first bunch of patches that prepare kernel to boot-time switching > > > > between paging modes. > > > > > > > > Please review and consider applying. > > > > > > Ping? > > > > Ingo, is there anything I can do to get review easier for you? > > Yeah, what is the conclusion on the sub-discussion of patch #2: > > [PATCH 2/6] mm/zsmalloc: Prepare to variable MAX_PHYSMEM_BITS > > ... do we want to skip it entirely and use the other 5 patches? Sorry for the too much late reply, Kirill. Yes, you can skip it. As Nitin said in that patch's thread, zsmalloc has assumed PFN_BIT is (BITS_PER_LONG - PAGE_SHIFT) so it already covers X86_5LEVEL well, I think. In summary, there is no need to change it. I hope it helps to merge this patchset series. Thanks.