From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755427AbdKBIMx (ORCPT ); Thu, 2 Nov 2017 04:12:53 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:60390 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755374AbdKBIMF (ORCPT ); Thu, 2 Nov 2017 04:12:05 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 7BD33607C9 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=sboyd@codeaurora.org Date: Thu, 2 Nov 2017 01:12:03 -0700 From: Stephen Boyd To: sean.wang@mediatek.com Cc: mturquette@baylibre.com, robh+dt@kernel.org, matthias.bgg@gmail.com, mark.rutland@arm.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Chen Zhong Subject: Re: [PATCH v2 3/4] clk: mediatek: add clock support for MT7622 SoC Message-ID: <20171102081203.GF11011@codeaurora.org> References: <9d8aa50c0e9f45e7a7fbb3e0682e7d8ed72a0205.1507174799.git.sean.wang@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <9d8aa50c0e9f45e7a7fbb3e0682e7d8ed72a0205.1507174799.git.sean.wang@mediatek.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/05, sean.wang@mediatek.com wrote: > From: Sean Wang > > Add all supported clocks exported from every susbystem found on MT7622 SoC > such as topckgen, apmixedsys, infracfg, pericfg , pciessys, ssusbsys, > ethsys and audsys. > > Signed-off-by: Chen Zhong > Signed-off-by: Sean Wang > --- Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project