From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754060AbdKJTbZ (ORCPT ); Fri, 10 Nov 2017 14:31:25 -0500 Received: from mga07.intel.com ([134.134.136.100]:56677 "EHLO mga07.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754029AbdKJTbW (ORCPT ); Fri, 10 Nov 2017 14:31:22 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.44,375,1505804400"; d="scan'208";a="172185750" Subject: [PATCH 03/30] x86/mm: Document X86_CR4_PGE toggling behavior To: linux-kernel@vger.kernel.org Cc: linux-mm@kvack.org, dave.hansen@linux.intel.com, moritz.lipp@iaik.tugraz.at, daniel.gruss@iaik.tugraz.at, michael.schwarz@iaik.tugraz.at, richard.fellner@student.tugraz.at, luto@kernel.org, torvalds@linux-foundation.org, keescook@google.com, hughd@google.com, x86@kernel.org From: Dave Hansen Date: Fri, 10 Nov 2017 11:31:03 -0800 References: <20171110193058.BECA7D88@viggo.jf.intel.com> In-Reply-To: <20171110193058.BECA7D88@viggo.jf.intel.com> Message-Id: <20171110193103.EC2A1EEE@viggo.jf.intel.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Dave Hansen The comment says it all here. The problem here is that the X86_CR4_PGE bit affects all PCIDs in a way that is totally obscure. This makes it easier for someone to grep for PCID-related code and documents the expected hardware behavior. Signed-off-by: Dave Hansen Cc: Moritz Lipp Cc: Daniel Gruss Cc: Michael Schwarz Cc: Richard Fellner Cc: Andy Lutomirski Cc: Linus Torvalds Cc: Kees Cook Cc: Hugh Dickins Cc: x86@kernel.org --- b/arch/x86/include/asm/tlbflush.h | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff -puN arch/x86/include/asm/tlbflush.h~kaiser-prep-document-cr4-pge-behavior arch/x86/include/asm/tlbflush.h --- a/arch/x86/include/asm/tlbflush.h~kaiser-prep-document-cr4-pge-behavior 2017-11-10 11:22:06.079244957 -0800 +++ b/arch/x86/include/asm/tlbflush.h 2017-11-10 11:22:06.082244957 -0800 @@ -257,10 +257,12 @@ static inline void __native_flush_tlb_gl WARN_ON_ONCE(!(cr4 & X86_CR4_PGE)); /* - * Architecturally, any _change_ to X86_CR4_PGE will fully flush the - * TLB of all entries including all entries in all PCIDs and all - * global pages. Make sure that we _change_ the bit, regardless of + * Architecturally, any _change_ to X86_CR4_PGE will fully flush + * all entries. Make sure that we _change_ the bit, regardless of * whether we had X86_CR4_PGE set in the first place. + * + * Note that just toggling PGE *also* flushes all entries from all + * PCIDs, regardless of the state of X86_CR4_PCIDE. */ native_write_cr4(cr4 ^ X86_CR4_PGE); _