From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756337AbdKOBFQ (ORCPT ); Tue, 14 Nov 2017 20:05:16 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:36488 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754173AbdKOBFH (ORCPT ); Tue, 14 Nov 2017 20:05:07 -0500 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 1FB6060719 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=sboyd@codeaurora.org Date: Tue, 14 Nov 2017 17:05:05 -0800 From: Stephen Boyd To: Shanker Donthineni Cc: Will Deacon , Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-efi@vger.kernel.org, Ard Biesheuvel , Matt Fleming , Catalin Marinas , linux-kernel@vger.kernel.org, James Morse , Robin Murphy , kvmarm@lists.cs.columbia.edu, Christoffer Dall Subject: Re: [PATCH v3 2/2] arm64: Add software workaround for Falkor erratum 1041 Message-ID: <20171115010505.GO11955@codeaurora.org> References: <1510537359-9978-1-git-send-email-shankerd@codeaurora.org> <1510537359-9978-3-git-send-email-shankerd@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1510537359-9978-3-git-send-email-shankerd@codeaurora.org> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/12, Shanker Donthineni wrote: > The ARM architecture defines the memory locations that are permitted > to be accessed as the result of a speculative instruction fetch from > an exception level for which all stages of translation are disabled. > Specifically, the core is permitted to speculatively fetch from the > 4KB region containing the current program counter 4K and next 4K. > > When translation is changed from enabled to disabled for the running > exception level (SCTLR_ELn[M] changed from a value of 1 to 0), the > Falkor core may errantly speculatively access memory locations outside > of the 4KB region permitted by the architecture. The errant memory > access may lead to one of the following unexpected behaviors. > > 1) A System Error Interrupt (SEI) being raised by the Falkor core due > to the errant memory access attempting to access a region of memory > that is protected by a slave-side memory protection unit. > 2) Unpredictable device behavior due to a speculative read from device > memory. This behavior may only occur if the instruction cache is > disabled prior to or coincident with translation being changed from > enabled to disabled. > > The conditions leading to this erratum will not occur when either of the > following occur: > 1) A higher exception level disables translation of a lower exception level > (e.g. EL2 changing SCTLR_EL1[M] from a value of 1 to 0). > 2) An exception level disabling its stage-1 translation if its stage-2 > translation is enabled (e.g. EL1 changing SCTLR_EL1[M] from a value of 1 > to 0 when HCR_EL2[VM] has a value of 1). > > To avoid the errant behavior, software must execute an ISB immediately > prior to executing the MSR that will change SCTLR_ELn[M] from 1 to 0. > This also applies to Kryo CPUs. I have a patch[1] for the 1003 Falkor errata that adds the Kryo MIDR check which can also be used for this errata. [1] https://patchwork.kernel.org/patch/10048987/ -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project