From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932507AbdKOVBd (ORCPT ); Wed, 15 Nov 2017 16:01:33 -0500 Received: from mail-wm0-f68.google.com ([74.125.82.68]:37924 "EHLO mail-wm0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934236AbdKOVBU (ORCPT ); Wed, 15 Nov 2017 16:01:20 -0500 X-Google-Smtp-Source: AGs4zMajs8zi/GWjGQUo5R/xMGlSCSvi8UJEocx3V7XTcIxl13hMuXNM0x/EoD9LRKDwiTV/oYohfA== Date: Wed, 15 Nov 2017 22:01:11 +0100 From: Andrea Parri To: Peter Zijlstra Cc: Alan Stern , Will Deacon , "Reshetova, Elena" , "linux-kernel@vger.kernel.org" , "gregkh@linuxfoundation.org" , "keescook@chromium.org" , "tglx@linutronix.de" , "mingo@redhat.com" , "ishkamiel@gmail.com" , Paul McKenney , boqun.feng@gmail.com, dhowells@redhat.com, david@fromorbit.com Subject: Re: [PATCH] refcount: provide same memory ordering guarantees as in atomic_t Message-ID: <20171115205823.GA2608@andrea> References: <20171115180540.GQ19071@arm.com> <20171115200307.ns4ja7xjwhunen65@hirez.programming.kicks-ass.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20171115200307.ns4ja7xjwhunen65@hirez.programming.kicks-ass.net> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Nov 15, 2017 at 09:03:07PM +0100, Peter Zijlstra wrote: > On Wed, Nov 15, 2017 at 02:15:19PM -0500, Alan Stern wrote: > > On Wed, 15 Nov 2017, Will Deacon wrote: > > > > > On Thu, Nov 02, 2017 at 04:21:56PM -0400, Alan Stern wrote: > > > > I was trying to think of something completely different. If you have a > > > > release/acquire to the same address, it creates a happens-before > > > > ordering: > > > > > > > > Access x > > > > Release a > > > > Acquire a > > > > Access y > > > > > > > > Here is the access to x happens-before the access to y. This is true > > > > even on x86, even in the presence of forwarding -- the CPU still has to > > > > execute the instructions in order. But if the release and acquire are > > > > to different addresses: > > > > > > > > Access x > > > > Release a > > > > Acquire b > > > > Access y > > > > > > > > then there is no happens-before ordering for x and y -- the CPU can > > > > execute the last two instructions before the first two. x86 and > > > > PowerPC won't do this, but I believe ARMv8 can. (Please correct me if > > > > it can't.) > > > > > > Release/Acquire are RCsc on ARMv8, so they are ordered irrespective of > > > address. > > > > Ah, okay, thanks. > > > > In any case, we have considered removing this ordering constraint > > (store-release followed by load-acquire for the same location) from the > > Linux-kernel memory model. > > Why? Its a perfectly sensible construct. > > > I'm not aware of any code in the kernel that depends on it. Do any of > > you happen to know of any examples? > > All locks? Something like: > > spin_lock(&x) > /* foo */ > spin_unlock(&x) > spin_lock(&x) > /* bar */ > spin_unlock(&x); > > Has a fairly high foo happens-before bar expectation level. > > And in specific things like: > > 135e8c9250dd5 > ecf7d01c229d1 > > which use the release of rq->lock paired with the next acquire of the > same rq->lock to match with an smp_rmb(). Those cycles are currently forbidden by LKMM _when_ you consider the smp_mb__after_spinlock() from schedule(). See rfi-rel-acq-is-not-mb from my previous email and Alan's remarks about cumul-fence. Andrea