From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934046AbdKPAzN (ORCPT ); Wed, 15 Nov 2017 19:55:13 -0500 Received: from mail-pg0-f53.google.com ([74.125.83.53]:49411 "EHLO mail-pg0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753353AbdKPAzF (ORCPT ); Wed, 15 Nov 2017 19:55:05 -0500 X-Google-Smtp-Source: AGs4zMbGylp3POAONtpdVxeenD7drJROhH/peyIIBlnQk8aPl7IGxDW9PzKbV6OQrE5LmSm3vg53nw== Date: Thu, 16 Nov 2017 08:54:41 +0800 From: Shawn Guo To: Jiancheng Xue Cc: sboyd@codeaurora.org, mturquette@baylibre.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, hermit.wangheming@hisilicon.com, project-aspen-dev@linaro.org Subject: Re: [PATCH 0/3] add more clock definitions for hi3798cv200-poplar board Message-ID: <20171116005438.GH11163@dragon> References: <1508324429-6012-1-git-send-email-xuejiancheng@hisilicon.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1508324429-6012-1-git-send-email-xuejiancheng@hisilicon.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Stephen, On Wed, Oct 18, 2017 at 07:00:26AM -0400, Jiancheng Xue wrote: > Add more clock definitions for hi3798cv200-poplar board. > > Younian Wang (1): > clk: hisilicon: correct ir clock rate for hi3798cv200 SoC > > tianshuliang (2): > clk: hisilicon: add hisi phase clock support > clk: hisilicon: add emmc sample and drive clock for hi3798cv200 SoC Since you haven't applied this series, I will update it with a few more patches added. I assume it's late for 4.15 merge window anyway, so I intend to maintain a branch for all those Hi3798CV200 clock patches. After the patches are properly reviewed, I can rebase the branch to 4.15-rc and then ask you to pull for next merge window. Sounds good to you? Shawn