From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934796AbdKPGrs (ORCPT ); Thu, 16 Nov 2017 01:47:48 -0500 Received: from mail-pg0-f67.google.com ([74.125.83.67]:47720 "EHLO mail-pg0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934779AbdKPGrl (ORCPT ); Thu, 16 Nov 2017 01:47:41 -0500 X-Google-Smtp-Source: AGs4zMbjpDKGovmEDB9H2gdeyhgKBM8pEd1QoMTxspaxy0YfzlVDK7VCDBjDhQYQn74UlDBb9hPBLQ== Date: Thu, 16 Nov 2017 14:47:16 +0800 From: Shawn Guo To: Jiancheng Xue Cc: hermit.wangheming@hisilicon.com, sboyd@codeaurora.org, mturquette@baylibre.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, project-aspen-dev@linaro.org, tianshuliang Subject: Re: [project-aspen-dev] Re: [PATCH 1/3] clk: hisilicon: add hisi phase clock support Message-ID: <20171116064715.GC24950@dragon> References: <1508324429-6012-1-git-send-email-xuejiancheng@hisilicon.com> <1508324429-6012-2-git-send-email-xuejiancheng@hisilicon.com> <20171116023131.GI11163@dragon> <78d5a8dc-5009-332b-e888-c37dc68bac91@hisilicon.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <78d5a8dc-5009-332b-e888-c37dc68bac91@hisilicon.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Nov 16, 2017 at 11:40:18AM +0800, Jiancheng Xue wrote: > >> +struct clk_hisi_phase { > >> + struct clk_hw hw; > >> + void __iomem *reg; > >> + u32 *phase_values; > >> + u32 *phase_regs; > >> + u8 phase_num; > > > > I do not think this value-reg table is necessary, as the register value > > maps to phase degree in a way that is easy for programming, i.e. degree > > increases 45 with register value increases one. > > > We expected that this interface could be more generic. That means it can > be also used in other maps instances. Okay, if you think there will be some case using different programming model, I'm fine with it. Shawn