From: Nadav Amit <namit@vmware.com>
To: <linux-kernel@vger.kernel.org>, <linux-edac@vger.kernel.org>
Cc: <nadav.amit@gmail.com>, Nadav Amit <namit@vmware.com>,
Andy Lutomirski <luto@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, "H. Peter Anvin" <hpa@zytor.com>,
<x86@kernel.org>
Subject: [PATCH v2 1/2] x86: refactor CR4 setting and shadow write
Date: Fri, 24 Nov 2017 19:29:06 -0800 [thread overview]
Message-ID: <20171125032907.2241-2-namit@vmware.com> (raw)
In-Reply-To: <20171125032907.2241-1-namit@vmware.com>
Refactor the write to CR4 and its shadow value. This is done in
preparation for the addition of an assertion to check that IRQs are
disabled during CR4 update.
No functional change.
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: x86@kernel.org
Signed-off-by: Nadav Amit <namit@vmware.com>
---
arch/x86/include/asm/tlbflush.h | 24 +++++++++++-------------
1 file changed, 11 insertions(+), 13 deletions(-)
diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h
index 509046cfa5ce..e736f7f0ba92 100644
--- a/arch/x86/include/asm/tlbflush.h
+++ b/arch/x86/include/asm/tlbflush.h
@@ -173,17 +173,20 @@ static inline void cr4_init_shadow(void)
this_cpu_write(cpu_tlbstate.cr4, __read_cr4());
}
+static inline void __cr4_set(unsigned long cr4)
+{
+ this_cpu_write(cpu_tlbstate.cr4, cr4);
+ __write_cr4(cr4);
+}
+
/* Set in this cpu's CR4. */
static inline void cr4_set_bits(unsigned long mask)
{
unsigned long cr4;
cr4 = this_cpu_read(cpu_tlbstate.cr4);
- if ((cr4 | mask) != cr4) {
- cr4 |= mask;
- this_cpu_write(cpu_tlbstate.cr4, cr4);
- __write_cr4(cr4);
- }
+ if ((cr4 | mask) != cr4)
+ __cr4_set(cr4 | mask);
}
/* Clear in this cpu's CR4. */
@@ -192,11 +195,8 @@ static inline void cr4_clear_bits(unsigned long mask)
unsigned long cr4;
cr4 = this_cpu_read(cpu_tlbstate.cr4);
- if ((cr4 & ~mask) != cr4) {
- cr4 &= ~mask;
- this_cpu_write(cpu_tlbstate.cr4, cr4);
- __write_cr4(cr4);
- }
+ if ((cr4 & ~mask) != cr4)
+ __cr4_set(cr4 & ~mask);
}
static inline void cr4_toggle_bits(unsigned long mask)
@@ -204,9 +204,7 @@ static inline void cr4_toggle_bits(unsigned long mask)
unsigned long cr4;
cr4 = this_cpu_read(cpu_tlbstate.cr4);
- cr4 ^= mask;
- this_cpu_write(cpu_tlbstate.cr4, cr4);
- __write_cr4(cr4);
+ __cr4_set(cr4 ^ mask);
}
/* Read the CR4 shadow. */
--
2.14.1
next prev parent reply other threads:[~2017-11-25 3:44 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-11-25 3:29 [PATCH v2 0/2] x86: disable IRQs during CR4 changes Nadav Amit
2017-11-25 3:29 ` Nadav Amit [this message]
2017-11-25 12:37 ` [tip:x86/urgent] x86/tlb: Refactor CR4 setting and shadow write tip-bot for Nadav Amit
2017-11-25 3:29 ` [PATCH v2 2/2] x86: disable IRQs before changing CR4 Nadav Amit
2017-11-25 10:36 ` Thomas Gleixner
2017-11-25 17:20 ` Nadav Amit
2017-11-25 17:25 ` Thomas Gleixner
2017-11-25 17:31 ` Nadav Amit
2017-11-25 12:38 ` [tip:x86/urgent] x86/tlb: Disable interrupts when " tip-bot for Nadav Amit
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