Re: [PATCH v2 2/2] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver

Philippe Ombredanne
2017-12-07T21:47:49Z

Dear Dhaval,

On Thu, Dec 7, 2017 at 10:31 PM, Dhaval Shah <dhaval.shah@xilinx.com> wrote:
> Xilinx ZYNQMP logicoreIP Init driver is based on the new
> LogiCoreIP design created. This driver provides the processing system
> and programmable logic isolation. Set the frequency based on the clock
> information get from the logicoreIP register set.
>
> It is put in drivers/misc as there is no subsystem for this logicoreIP.
>
> Signed-off-by: Dhaval Shah <dshah@xilinx.com>
> ---
> Changes since v2:
> * Removed the "default n" from the Kconfig
> * More help text added to explain more about the logicoreIP driver
> * SPDX id is relocated at top of the file with // style comment
> * Removed the export API and header file and make it a single driver
> which provides logocoreIP init.
> * Provide the information in commit message as well for the why driver
> in drivers/misc.

Thank you for the SPDX comments updates.

Acked-by: Philippe Ombredanne <pombredanne@nexb.com>

--
Cordially
Philippe Ombredanne