From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756391AbeARNqB (ORCPT ); Thu, 18 Jan 2018 08:46:01 -0500 Received: from mail.free-electrons.com ([62.4.15.54]:35391 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755840AbeARNqA (ORCPT ); Thu, 18 Jan 2018 08:46:00 -0500 Date: Thu, 18 Jan 2018 14:45:48 +0100 From: Boris Brezillon To: Eric Anholt Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] drm/vc4: Flush the caches before the bin jobs, as well. Message-ID: <20180118144548.3db88ecf@bbrezillon> In-Reply-To: <20171221221722.23809-1-eric@anholt.net> References: <20171221221722.23809-1-eric@anholt.net> X-Mailer: Claws Mail 3.14.1 (GTK+ 2.24.31; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 21 Dec 2017 14:17:22 -0800 Eric Anholt wrote: > If the frame samples from a render target that was just written, its > cache flush during the binning step may have occurred before the > previous frame's RCL was completed. Flush the texture caches again > before starting each RCL job to make sure that the sampling of the > previous RCL's output is correct. > > Fixes flickering in the top left of 3DMMES Taiji. > > Signed-off-by: Eric Anholt > Fixes: ca26d28bbaa3 ("drm/vc4: improve throughput by pipelining binning and rendering jobs") Reviewed-by: Boris Brezillon > --- > drivers/gpu/drm/vc4/vc4_gem.c | 21 +++++++++++++++++++++ > 1 file changed, 21 insertions(+) > > diff --git a/drivers/gpu/drm/vc4/vc4_gem.c b/drivers/gpu/drm/vc4/vc4_gem.c > index 6c32c89a83a9..afa7fe21b35e 100644 > --- a/drivers/gpu/drm/vc4/vc4_gem.c > +++ b/drivers/gpu/drm/vc4/vc4_gem.c > @@ -436,6 +436,19 @@ vc4_flush_caches(struct drm_device *dev) > VC4_SET_FIELD(0xf, V3D_SLCACTL_ICC)); > } > > +static void > +vc4_flush_texture_caches(struct drm_device *dev) > +{ > + struct vc4_dev *vc4 = to_vc4_dev(dev); > + > + V3D_WRITE(V3D_L2CACTL, > + V3D_L2CACTL_L2CCLR); > + > + V3D_WRITE(V3D_SLCACTL, > + VC4_SET_FIELD(0xf, V3D_SLCACTL_T1CC) | > + VC4_SET_FIELD(0xf, V3D_SLCACTL_T0CC)); > +} > + > /* Sets the registers for the next job to be actually be executed in > * the hardware. > * > @@ -474,6 +487,14 @@ vc4_submit_next_render_job(struct drm_device *dev) > if (!exec) > return; > > + /* A previous RCL may have written to one of our textures, and > + * our full cache flush at bin time may have occurred before > + * that RCL completed. Flush the texture cache now, but not > + * the instructions or uniforms (since we don't write those > + * from an RCL). > + */ > + vc4_flush_texture_caches(dev); > + > submit_cl(dev, 1, exec->ct1ca, exec->ct1ea); > } >