From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AH8x224SJbIOnYSY/OAJ7cd/8glqYHyPeF2O6TyCtF3PmuN99cXEI5/7232Zh30xBZnsgAAzNm0X ARC-Seal: i=1; a=rsa-sha256; t=1516610485; cv=none; d=google.com; s=arc-20160816; b=cTF7NVEBGBxovynEhE9616Jtg+bSkhs+icxwJphvFAS1jPWfCMuvkEwFTC1he0ePij FH9/d1wYBjxXN/4JJRQDa/7FKjR/SWiIe3kpe/HKu7fM8XYm7u+3gRXZiJ0x3oa+58IM CZK4mbK2j0lKEmkgiH8N8WBk3SIgRSx04T17guNq5C7GOyRgUEuizrRms4g+407zVMFq bRIIrFzButJq6FPNsNPyt0Kqznx+qqi9cF3DVn298LNRrIRbC8cmYvWI3Y9ZlVIGed0o qYaRIpjQDYp3rcTedrSAKHVGoBokr0bpxFpnsTT/XJRuN0bmAxPVRc9m5XkW/3P0PCIB jG2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:user-agent:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=UD4H1liP1AfOhCjtjGTl1HuQinR/qH6hwllfj9dj48g=; b=UIXv5LD5AP4KDHk2811nAyk5FdK/uJl4ieqLKUt5g4hqPNxC5LKFV07bZCA22XgWIc K9lXUlp+NwOWCF0taw/6ZzR9rgHmDrW9/AT2qOsceHhCK1XggQyFz7wQijmG6QvQxt+Z mB6lG2q0KwmJwgQmt/KK3WS7hqIHEWfmy0Yh6zzGx24FjqilK43fD5cb7Y4L12VmdQ+5 KsH+EWqKbsrRNJCx5AthniUiV14OBp9TmLRXVMgyQ58vEyShyllfcZoKu5/s0Q4RuZ7C T9t1WzSYr5YrpBeaP0r/mZ63pSRJtdNO5NNvQf38I6uw8IN/3+tZ1lyFDK8V59AidxxQ c9vg== ARC-Authentication-Results: i=1; mx.google.com; spf=softfail (google.com: domain of transitioning gregkh@linuxfoundation.org does not designate 90.92.71.90 as permitted sender) smtp.mailfrom=gregkh@linuxfoundation.org Authentication-Results: mx.google.com; spf=softfail (google.com: domain of transitioning gregkh@linuxfoundation.org does not designate 90.92.71.90 as permitted sender) smtp.mailfrom=gregkh@linuxfoundation.org From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Tom Lendacky , Thomas Gleixner , "Reviewed-by: Borislav Petkov" , Peter Zijlstra , Tim Chen , Dave Hansen , Borislav Petkov , Dan Williams , Linus Torvalds , David Woodhouse , Paul Turner , Razvan Ghitulete , Greg Kroah-Hartman Subject: [PATCH 4.4 02/53] x86/cpu/AMD: Make LFENCE a serializing instruction Date: Mon, 22 Jan 2018 09:39:54 +0100 Message-Id: <20180122083910.411590683@linuxfoundation.org> X-Mailer: git-send-email 2.16.0 In-Reply-To: <20180122083910.299610926@linuxfoundation.org> References: <20180122083910.299610926@linuxfoundation.org> User-Agent: quilt/0.65 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-LABELS: =?utf-8?b?IlxcU2VudCI=?= X-GMAIL-THRID: =?utf-8?q?1590281356930570116?= X-GMAIL-MSGID: =?utf-8?q?1590281356930570116?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: 4.4-stable review patch. If anyone has any objections, please let me know. ------------------ From: Tom Lendacky commit e4d0e84e490790798691aaa0f2e598637f1867ec upstream. To aid in speculation control, make LFENCE a serializing instruction since it has less overhead than MFENCE. This is done by setting bit 1 of MSR 0xc0011029 (DE_CFG). Some families that support LFENCE do not have this MSR. For these families, the LFENCE instruction is already serializing. Signed-off-by: Tom Lendacky Signed-off-by: Thomas Gleixner Reviewed-by: Reviewed-by: Borislav Petkov Cc: Peter Zijlstra Cc: Tim Chen Cc: Dave Hansen Cc: Borislav Petkov Cc: Dan Williams Cc: Linus Torvalds Cc: Greg Kroah-Hartman Cc: David Woodhouse Cc: Paul Turner Link: https://lkml.kernel.org/r/20180108220921.12580.71694.stgit@tlendack-t1.amdoffice.net Signed-off-by: Razvan Ghitulete Signed-off-by: Greg Kroah-Hartman --- arch/x86/include/asm/msr-index.h | 2 ++ arch/x86/kernel/cpu/amd.c | 10 ++++++++++ 2 files changed, 12 insertions(+) --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -330,6 +330,8 @@ #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL #define FAM10H_MMIO_CONF_BASE_SHIFT 20 #define MSR_FAM10H_NODE_ID 0xc001100c +#define MSR_F10H_DECFG 0xc0011029 +#define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT 1 /* K8 MSRs */ #define MSR_K8_TOP_MEM1 0xc001001a --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -746,6 +746,16 @@ static void init_amd(struct cpuinfo_x86 set_cpu_cap(c, X86_FEATURE_K8); if (cpu_has_xmm2) { + /* + * A serializing LFENCE has less overhead than MFENCE, so + * use it for execution serialization. On families which + * don't have that MSR, LFENCE is already serializing. + * msr_set_bit() uses the safe accessors, too, even if the MSR + * is not present. + */ + msr_set_bit(MSR_F10H_DECFG, + MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT); + /* MFENCE stops RDTSC speculation */ set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); }