From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751421AbeAWQsf (ORCPT ); Tue, 23 Jan 2018 11:48:35 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:44542 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750994AbeAWQse (ORCPT ); Tue, 23 Jan 2018 11:48:34 -0500 From: Ivan Mikhaylov To: "David S . Miller" , Christian Lamparter , Rob Herring Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/2] net/ibm/emac: wrong bit is used for STA control register write Date: Tue, 23 Jan 2018 19:48:25 +0300 X-Mailer: git-send-email 2.10.1 (Apple Git-78) X-MIMETrack: Itemize by SMTP Server on D06ML001/06/M/IBM(Release 9.0.1FP8HF179 | April 20, 2017) at 23/01/2018 16:48:26, Serialize by Router on D06ML001/06/M/IBM(Release 9.0.1FP8HF179 | April 20, 2017) at 23/01/2018 16:48:26, Serialize complete at 23/01/2018 16:48:26 X-TNEFEvaluated: 1 X-TM-AS-GCONF: 00 x-cbid: 18012316-0016-0000-0000-0000051AF9A5 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18012316-0017-0000-0000-000028578026 Message-Id: <20180123164825.48159-1-ivan@de.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2018-01-23_05:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1801230230 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org STA control register has areas of mode and opcodes for opeations. 18 bit is using for mode selection, where 0 is old MIO/MDIO access method and 1 is indirect access mode. 19-20 bits are using for setting up read/write operation(STA opcodes). In current state 'read' is set into old MIO/MDIO mode with 19 bit and write operation is set into 18 bit which is mode selection, not a write operation. To correlate write with read we set it into 20 bit. All those bit operations are MSB 0 based. Signed-off-by: Ivan Mikhaylov --- drivers/net/ethernet/ibm/emac/emac.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/net/ethernet/ibm/emac/emac.h b/drivers/net/ethernet/ibm/emac/emac.h index d0a0e3b..c26d263 100644 --- a/drivers/net/ethernet/ibm/emac/emac.h +++ b/drivers/net/ethernet/ibm/emac/emac.h @@ -244,7 +244,7 @@ struct emac_regs { #define EMAC_STACR_PHYE 0x00004000 #define EMAC_STACR_STAC_MASK 0x00003000 #define EMAC_STACR_STAC_READ 0x00001000 -#define EMAC_STACR_STAC_WRITE 0x00002000 +#define EMAC_STACR_STAC_WRITE 0x00000800 #define EMAC_STACR_OPBC_MASK 0x00000C00 #define EMAC_STACR_OPBC_50 0x00000000 #define EMAC_STACR_OPBC_66 0x00000400 -- 1.7.1