Re: [PATCH v2 2/5] x86/cpufeatures: Add Intel feature bits for Speculation Control

Woodhouse, David
2018-01-24T01:23:58Z

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On Tue, 2018-01-23 at 10:43 -0800, Dave Hansen wrote:
> On 01/23/2018 08:52 AM, David Woodhouse wrote:
> >
> > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> > index 7b25cf3..0a51070 100644
> > --- a/arch/x86/include/asm/cpufeatures.h
> > +++ b/arch/x86/include/asm/cpufeatures.h
> > @@ -320,6 +320,9 @@
> >  /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */
> >  #define X86_FEATURE_AVX512_4VNNIW    (18*32+ 2) /* AVX-512 Neural Network Instructions */
> >  #define X86_FEATURE_AVX512_4FMAPS    (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */
> > +#define X86_FEATURE_SPEC_CTRL                (18*32+26) /* Speculation Control (IBRS + IBPB) */
> > +#define X86_FEATURE_STIBP            (18*32+27) /* Single Thread Indirect Branch Predictors */
> > +#define X86_FEATURE_ARCH_CAPABILITIES        (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */
>
> Should we be adding flags (STIBP) for which we currently have no user in
> the kernel?

They're in an existing word (now) so it costs us absolutely nothing to
do so. And they'll be exposed to KVM guests in imminent patches if
nothing else.

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