From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751741AbeAZCto (ORCPT ); Thu, 25 Jan 2018 21:49:44 -0500 Received: from mx1.redhat.com ([209.132.183.28]:48984 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751452AbeAZCtn (ORCPT ); Thu, 25 Jan 2018 21:49:43 -0500 Date: Fri, 26 Jan 2018 04:49:41 +0200 From: "Michael S. Tsirkin" To: Jason Wang Cc: Paolo Bonzini , Radim =?utf-8?B?S3LEjW3DocWZ?= , Liran Alon , vkuznets@redhat.com, x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Subject: Re: [PATCH] x86/kvm: disable fast MMIO when running nested Message-ID: <20180126044919-mutt-send-email-mst@kernel.org> References: <6690c53c-fc99-44ea-9090-6e7438c1bc98@default> <20180125141620.GA7663@flask> <2039380511.2539348.1516891762406.JavaMail.zimbra@redhat.com> <20180125185431-mutt-send-email-mst@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jan 26, 2018 at 10:41:58AM +0800, Jason Wang wrote: > > > On 2018年01月26日 01:11, Michael S. Tsirkin wrote: > > On Thu, Jan 25, 2018 at 09:49:22AM -0500, Paolo Bonzini wrote: > > > > > Michael and Jason, any progress on implementing a fast virtio mechanism > > > > > that doesn't rely on undefined behavior? > > > > > > > > > > (Encode writing instruction length into last 4 bits of MMIO address, > > > > > side-channel say that accesses to the MMIO area always use certain > > > > > instruction length, use hypercall, ...) > > > > > > > > > > Thanks. > > > > No progress from my side. But we can use PIO for virtio 1.0 and it's > > > > faster than fast MMIO (qemu supports modern pio notification bar, we can > > > > make it as default). It looks to me that neither encoding nor hypercall > > > > will work for real hardware virtio device. > > > Encoding the instruction length would work, the h/w virtio devices would > > > just ignore it. But... it is really ugly. > > > > > > Using PIO would be a small step backwards for PCIe. As long as the device > > > only needs *one* notification register (either MMIO or PIO) to initialize > > > successfully, it's okay. Then if there is no PIO space you'd just fall back > > > to the slower MMIO notification. > > > > > > Paolo > > A bigger issue for PIO is it's causing exits for hw devices. > > > > > > Just to make sure I understand. For exits you mean vmexit? I believe MMIO > will cause vmexit too. > > Thanks Not with an assigned device where the PTE is marked as present, it won't. -- MST