From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751814AbeAZPdV (ORCPT ); Fri, 26 Jan 2018 10:33:21 -0500 Received: from foss.arm.com ([217.140.101.70]:49670 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751405AbeAZPdU (ORCPT ); Fri, 26 Jan 2018 10:33:20 -0500 Date: Fri, 26 Jan 2018 15:33:15 +0000 From: Dave Martin To: Suzuki K Poulose Cc: linux-arm-kernel@lists.infradead.org, mark.rutland@arm.com, ckadabi@codeaurora.org, ard.biesheuvel@linaro.org, marc.zyngier@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, jnair@caviumnetworks.com Subject: Re: [PATCH 16/16] arm64: Add work around for Arm Cortex-A55 Erratum 1024718 Message-ID: <20180126153314.GW5862@e103592.cambridge.arm.com> References: <20180123122809.16269-1-suzuki.poulose@arm.com> <20180123122809.16269-17-suzuki.poulose@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20180123122809.16269-17-suzuki.poulose@arm.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Jan 23, 2018 at 12:28:09PM +0000, Suzuki K Poulose wrote: > Some variants of the Arm Cortex-55 cores (r0p0, r0p1, r1p0) suffer > from an erratum 1024718, which causes incorrect updates when DBM/AP > bits in a page table entry is modified without a break-before-make > sequence. The work around is to skip enabling the hardware DBM feature > on the affected cores. The hardware Access Flag management features > is not affected. > > Signed-off-by: Suzuki K Poulose > --- > Documentation/arm64/silicon-errata.txt | 1 + > arch/arm64/Kconfig | 14 ++++++++++++++ > arch/arm64/kernel/cpufeature.c | 14 +++++++++++++- > 3 files changed, 28 insertions(+), 1 deletion(-) [...] > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index 8af755b8219d..64f1e911c6af 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -914,9 +914,21 @@ static inline void __cpu_enable_hw_dbm(void) > isb(); > } > > +static bool cpu_has_erratum_1024718(void) > +{ > + static const struct midr_range __maybe_unused cpus[] = { Do you need __maybe_unused? If #ifdef were used here then __maybe_unused would be needed, but I thought that if code is optimised out instead of conditionally copiled, this didn't apply. > + MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0 > + {}, > + }; > + > + return IS_ENABLED(CONFIG_ARM64_ERRATUM_1024718) && > + is_midr_in_range_list(read_cpuid_id(), cpus); Why have a list with just one entry? Do you expect more entries over time? [...] Cheers ---Dave