From: Stephen Boyd <sboyd@codeaurora.org>
To: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: linux-clk@vger.kernel.org,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Joel Stanley <joel.stanley@au1.ibm.com>
Subject: Re: [PATCH] clk: aspeed: Handle inverse polarity of USB port 1 clock gate
Date: Fri, 26 Jan 2018 16:33:39 -0800 [thread overview]
Message-ID: <20180127003339.GG28313@codeaurora.org> (raw)
In-Reply-To: <1515736081.31850.88.camel@kernel.crashing.org>
On 01/12, Benjamin Herrenschmidt wrote:
> The USB port 1 clock gate control has an inversed polarity
> from all the other clock gates in the chip. This makes the
> aspeed_clk_{enable,disable} functions honor the flag
> CLK_GATE_SET_TO_DISABLE and set that flag appropriately
> so it's set for all clocks except USB port 1.
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> --
>
> I chose not to add a column to the table for that one special
> case. If future chips start growing more of these, we should
> consider adding this to the table instead.
>
> Without this, USB port 1 doesn't work properly with the new
> clk driver.
>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
prev parent reply other threads:[~2018-01-27 0:33 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-12 5:48 [PATCH] clk: aspeed: Handle inverse polarity of USB port 1 clock gate Benjamin Herrenschmidt
2018-01-15 16:49 ` Joel Stanley
2018-01-27 0:33 ` Stephen Boyd [this message]
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