From: Keith Busch <keith.busch@intel.com>
To: wenxiong@linux.vnet.ibm.com
Cc: linux-nvme@lists.infradead.org, axboe@fb.com,
linux-kernel@vger.kernel.org, wenxiong@us.ibm.com
Subject: Re: [PATCH V2]nvme-pci: Fixes EEH failure on ppc
Date: Wed, 7 Feb 2018 14:12:02 -0700 [thread overview]
Message-ID: <20180207211202.GD1337@localhost.localdomain> (raw)
In-Reply-To: <1518034178-26176-1-git-send-email-wenxiong@linux.vnet.ibm.com>
On Wed, Feb 07, 2018 at 02:09:38PM -0600, wenxiong@linux.vnet.ibm.com wrote:
> @@ -1189,6 +1183,12 @@ static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
> struct nvme_command cmd;
> u32 csts = readl(dev->bar + NVME_REG_CSTS);
>
> + /* If PCI error recovery process is happening, we cannot reset or
> + * the recovery mechanism will surely fail.
> + */
> + if (pci_channel_offline(to_pci_dev(dev->dev)))
> + return BLK_EH_RESET_TIMER;
So reading csts is what triggers EEH to be detected and get the channel
set offline? If so, don't we need a memory barrier before calling
pci_channel_offline? Otherwise it looks like the compiler optimization
could reorder these.
next prev parent reply other threads:[~2018-02-07 21:08 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-07 20:09 [PATCH V2]nvme-pci: Fixes EEH failure on ppc wenxiong
2018-02-07 21:12 ` Keith Busch [this message]
2018-02-08 16:39 ` Sagi Grimberg
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