Re: [PATCH v4 3/4] arm64: dts: sdm845: Add minimal dts/dtsi files for sdm845 SoC and MTP

Rajendra Nayak
2018-02-22T06:20:30Z

On 02/19/2018 10:06 PM, Marc Zyngier wrote:
> On Fri, 16 Feb 2018 11:35:02 +0530
> Rajendra Nayak <rnayak@codeaurora.org> wrote:
>
>> Add a skeletal sdm845 SoC dtsi and MTP board dts/dtsi files
>>
>> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
>> Reviewed-by: Doug Anderson <dianders@chromium.org>
>> ---
>> arch/arm64/boot/dts/qcom/Makefile | 1 +
>> arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 15 ++
>> arch/arm64/boot/dts/qcom/sdm845.dtsi | 277 ++++++++++++++++++++++++++++++++
>> 3 files changed, 293 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/qcom/sdm845-mtp.dts
>> create mode 100644 arch/arm64/boot/dts/qcom/sdm845.dtsi

[...]

>> +
>> + soc: soc {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0 0 0 0xffffffff>;
>> + compatible = "simple-bus";
>> +
>> + intc: interrupt-controller@17a00000 {
>> + compatible = "arm,gic-v3";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> + #interrupt-cells = <3>;
>> + interrupt-controller;
>> + #redistributor-regions = <1>;
>> + redistributor-stride = <0x0 0x20000>;
>> + reg = <0x17a00000 0x10000>, /* GICD */
>> + <0x17a60000 0x100000>; /* GICR * 8 */
>> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> + gic-its@17a40000 {
>> + compatible = "arm,gic-v3-its";
>> + msi-controller;
>> + #msi-cells = <1>;
>> + reg = <0x17a40000 0x20000>;
>> + status = "disabled";
>> + };
>> + };
>> +
>> + gcc: clock-controller@100000 {
>> + compatible = "qcom,gcc-sdm845";
>> + reg = <0x100000 0x1f0000>;
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + };
>> +
>> + tlmm: pinctrl@3400000 {
>> + compatible = "qcom,sdm845-pinctrl";
>> + reg = <0x03400000 0xc00000>;
>> + interrupts = <GIC_SPI 208 IRQ_TYPE_NONE>;
>
> Please do not use IRQ_TYPE_NONE, ever. It doesn't exist in the GIC
> binding. Set it to the actual trigger value.

Thanks Marc for the review. I fixed these up and did a respin.

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