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x-return-mx=pass smtp.domain=vger.kernel.org smtp.result=pass smtp_org.domain=kernel.org smtp_org.result=pass smtp_is_org_domain=no header.domain=gmail.com header.result=pass header_is_org_domain=yes Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1426738AbeCBK53 (ORCPT ); Fri, 2 Mar 2018 05:57:29 -0500 Received: from mail-qt0-f194.google.com ([209.85.216.194]:37992 "EHLO mail-qt0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1423941AbeCBK5X (ORCPT ); Fri, 2 Mar 2018 05:57:23 -0500 X-Google-Smtp-Source: AG47ELsWXC+1aO9aU1MbnYW0pnrRmzoUd5jDXYpDAI/DuSt02WfUcIS6RBCNXM+Y2098IJ2xkpZhhQ== Date: Fri, 2 Mar 2018 11:57:19 +0100 From: Thierry Reding To: sean.wang@mediatek.com Cc: matthias.bgg@gmail.com, linux-pwm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org, Zhi Mao , John Crispin Subject: Re: [PATCH v3] pwm: mediatek: fix up PWM4 and PWM5 malfunction on MT7623 Message-ID: <20180302105719.GC27178@ulmo> References: <051f401bcca48ece188023ccf10b2cedc7a25a64.1519891948.git.sean.wang@mediatek.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="6zdv2QT/q3FMhpsV" Content-Disposition: inline In-Reply-To: <051f401bcca48ece188023ccf10b2cedc7a25a64.1519891948.git.sean.wang@mediatek.com> User-Agent: Mutt/1.9.3 (2018-01-21) Sender: stable-owner@vger.kernel.org X-Mailing-List: stable@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-Mailing-List: linux-kernel@vger.kernel.org List-ID: --6zdv2QT/q3FMhpsV Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Mar 01, 2018 at 04:19:12PM +0800, sean.wang@mediatek.com wrote: > From: Sean Wang >=20 > Since the offset for both registers, PWMDWIDTH and PWMTHRES, used to > control PWM4 or PWM5 are distinct from the other PWMs, whose wrong > programming on PWM hardware causes waveform cannot be output as expected. > Thus, the patch adds the extra condition for fixing up the weird case to > let PWM4 or PWM5 able to work on MT7623. >=20 > v1 -> v2: use pwm45_fixup naming instead of pwm45_quirk > v2 -> v3: add more tags for Reviewed-by, Fixes, and Cc stable >=20 > Cc: stable@vger.kernel.org > Fixes: caf065f8fd58 ("pwm: Add MediaTek PWM support") > Signed-off-by: Sean Wang > Reviewed-by: Matthias Brugger > Cc: Zhi Mao > Cc: John Crispin > Cc: Matthias Brugger > --- > drivers/pwm/pwm-mediatek.c | 24 +++++++++++++++++++++--- > 1 file changed, 21 insertions(+), 3 deletions(-) >=20 > diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c [...] > @@ -151,9 +156,18 @@ static int mtk_pwm_config(struct pwm_chip *chip, str= uct pwm_device *pwm, > return -EINVAL; > } > =20 > + if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) { > + /* > + * PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES > + * from the other PWMs on MT7623. > + */ > + reg_width =3D PWM45DWIDTH_FIXUP; > + reg_thres =3D PWM45THRES_FIXUP; > + } I don't understand this. According to the condition above the above would also use the PWM[4,5] "fixup" register offsets with PWM[3]. Should the condition be pwm->hwpwm > 3? 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