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From: Thierry Reding <thierry.reding@gmail.com>
To: Marcel Ziswiler <marcel@ziswiler.com>
Cc: linux-tegra@vger.kernel.org, Dmitry Osipenko <digetx@gmail.com>,
	Marcel Ziswiler <marcel.ziswiler@toradex.com>,
	Stephen Boyd <sboyd@kernel.org>,
	linux-kernel@vger.kernel.org,
	Prashant Gaikwad <pgaikwad@nvidia.com>,
	Peter De Schrijver <pdeschrijver@nvidia.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Michael Turquette <mturquette@baylibre.com>,
	linux-clk@vger.kernel.org
Subject: Re: [PATCH] clk: tegra: fix pllu rate configuration
Date: Thu, 8 Mar 2018 15:57:43 +0100	[thread overview]
Message-ID: <20180308145743.GK3529@ulmo> (raw)
In-Reply-To: <20180222230451.15515-1-marcel@ziswiler.com>

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On Fri, Feb 23, 2018 at 12:04:51AM +0100, Marcel Ziswiler wrote:
> Turns out latest upstream U-Boot does not configure/enable pllu which
> leaves it at some default rate of 500 kHz:
> 
> root@apalis-t30:~# cat /sys/kernel/debug/clk/clk_summary | grep pll_u
>        pll_u                  3        3        0      500000          0
> 
> Of course this won't quite work leading to the following messages:
> 
> [    6.559593] usb 2-1: new full-speed USB device number 2 using tegra-
> ehci
> [   11.759173] usb 2-1: device descriptor read/64, error -110
> [   27.119453] usb 2-1: device descriptor read/64, error -110
> [   27.389217] usb 2-1: new full-speed USB device number 3 using tegra-
> ehci
> [   32.559454] usb 2-1: device descriptor read/64, error -110
> [   47.929777] usb 2-1: device descriptor read/64, error -110
> [   48.049658] usb usb2-port1: attempt power cycle
> [   48.759475] usb 2-1: new full-speed USB device number 4 using tegra-
> ehci
> [   59.349457] usb 2-1: device not accepting address 4, error -110
> [   59.509449] usb 2-1: new full-speed USB device number 5 using tegra-
> ehci
> [   70.069457] usb 2-1: device not accepting address 5, error -110
> [   70.079721] usb usb2-port1: unable to enumerate USB device
> 
> Fix this by actually allowing the rate also being set from within
> the Linux kernel.
> 
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> 
> ---
> 
>  drivers/clk/tegra/clk-pll.c | 2 ++
>  1 file changed, 2 insertions(+)

I'm aware of the discussion about how best to implement this, but this
seems like a reasonable fix until we have something better.

Peter, Jon: if you want to fix this more properly, please take point on
this.

Applied this to for-4.17/clk, thanks.

Thierry

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      parent reply	other threads:[~2018-03-08 14:57 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-02-22 23:04 [PATCH] clk: tegra: fix pllu rate configuration Marcel Ziswiler
2018-02-22 23:47 ` Stephen Warren
2018-02-23  6:28   ` Marcel Ziswiler
2018-02-26 12:42 ` Dmitry Osipenko
2018-02-26 23:04   ` Marcel Ziswiler
2018-02-27 11:59     ` Dmitry Osipenko
2018-02-28  9:36       ` Peter De Schrijver
2018-02-28 12:00         ` Dmitry Osipenko
2018-02-28 14:14           ` Peter De Schrijver
2018-02-28 17:20             ` Dmitry Osipenko
2018-03-01  7:41               ` Peter De Schrijver
2018-03-01 13:19                 ` Dmitry Osipenko
2018-03-01 13:44                   ` Dmitry Osipenko
2018-03-02  9:02                 ` Jon Hunter
2018-03-02 11:25                   ` Peter De Schrijver
2018-03-02  8:56 ` Jon Hunter
2018-03-08 14:57 ` Thierry Reding [this message]

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