From: Will Deacon <will.deacon@arm.com>
To: Shanker Donthineni <shankerd@codeaurora.org>
Cc: Robin Murphy <robin.murphy@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
linux-kernel <linux-kernel@vger.kernel.org>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
Catalin Marinas <catalin.marinas@arm.com>,
kvmarm <kvmarm@lists.cs.columbia.edu>,
Marc Zyngier <marc.zyngier@arm.com>,
Vikram Sethi <vikrams@codeaurora.org>,
Philip Elcan <pelcan@codeaurora.org>
Subject: Re: [PATCH v7] arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC
Date: Fri, 9 Mar 2018 13:48:13 +0000 [thread overview]
Message-ID: <20180309134813.GD15537@arm.com> (raw)
In-Reply-To: <1520434808-29703-1-git-send-email-shankerd@codeaurora.org>
On Wed, Mar 07, 2018 at 09:00:08AM -0600, Shanker Donthineni wrote:
> The DCache clean & ICache invalidation requirements for instructions
> to be data coherence are discoverable through new fields in CTR_EL0.
> The following two control bits DIC and IDC were defined for this
> purpose. No need to perform point of unification cache maintenance
> operations from software on systems where CPU caches are transparent.
>
> This patch optimize the three functions __flush_cache_user_range(),
> clean_dcache_area_pou() and invalidate_icache_range() if the hardware
> reports CTR_EL0.IDC and/or CTR_EL0.IDC. Basically it skips the two
> instructions 'DC CVAU' and 'IC IVAU', and the associated loop logic
> in order to avoid the unnecessary overhead.
Cheers, I've queued this for 4.17.
Will
prev parent reply other threads:[~2018-03-09 13:48 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-07 15:00 [PATCH v7] arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC Shanker Donthineni
2018-03-09 13:44 ` Mark Rutland
2018-03-09 13:47 ` Will Deacon
2018-03-09 13:48 ` Will Deacon [this message]
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