From: Peter Zijlstra <peterz@infradead.org>
To: "Liu, Changcheng" <changcheng.liu@intel.com>
Cc: tglx@linutronix.de, hpa@zytor.com, douly.fnst@cn.fujitsu.com,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] x86/ioapic: don't use unstable TSC to detect timer IRQ
Date: Tue, 20 Mar 2018 09:49:29 +0100 [thread overview]
Message-ID: <20180320084929.GP4043@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <20180320084255.GA187704@sofia>
On Tue, Mar 20, 2018 at 04:42:55PM +0800, Liu, Changcheng wrote:
> In rare case, the TSC is every unstable or can't sync with
> real time hardware clock.
However did you manage that? Please provide _FAR_ more details.
> diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h
> index cf5d53c..dcfc5b9 100644
> --- a/arch/x86/include/asm/tsc.h
> +++ b/arch/x86/include/asm/tsc.h
> @@ -17,6 +17,7 @@ typedef unsigned long long cycles_t;
>
> extern unsigned int cpu_khz;
> extern unsigned int tsc_khz;
> +extern int tsc_unstable;
>
> extern void disable_TSC(void);
>
> diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
> index 7c55387..0809ec6 100644
> --- a/arch/x86/kernel/apic/io_apic.c
> +++ b/arch/x86/kernel/apic/io_apic.c
> @@ -1643,7 +1643,7 @@ static int __init timer_irq_works(void)
> local_save_flags(flags);
> local_irq_enable();
>
> - if (boot_cpu_has(X86_FEATURE_TSC))
> + if (boot_cpu_has(X86_FEATURE_TSC) && !tsc_unstable)
> delay_with_tsc();
> else
> delay_without_tsc();
> diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
> index fb43027..27b1bae 100644
> --- a/arch/x86/kernel/tsc.c
> +++ b/arch/x86/kernel/tsc.c
> @@ -36,7 +36,8 @@ EXPORT_SYMBOL(tsc_khz);
> /*
> * TSC can be unstable due to cpufreq or due to unsynced TSCs
> */
> -static int __read_mostly tsc_unstable;
> +int __read_mostly tsc_unstable;
> +EXPORT_SYMBOL(tsc_unstable);
>
> /* native_sched_clock() is called before tsc_init(), so
> we must start with the TSC soft disabled to prevent
No, absolutely not. Even when the TSC is normally deemed unstable, which
typically means it is not sync'ed between cores, it is still perfectly
suitable to be used for delay loops.
next prev parent reply other threads:[~2018-03-20 8:49 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-20 8:42 [PATCH] x86/ioapic: don't use unstable TSC to detect timer IRQ Liu, Changcheng
2018-03-20 8:49 ` Peter Zijlstra [this message]
2018-03-20 8:58 ` Liu, Changcheng
2018-03-20 9:03 ` Thomas Gleixner
2018-03-20 9:09 ` Peter Zijlstra
2018-03-20 9:00 ` Thomas Gleixner
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20180320084929.GP4043@hirez.programming.kicks-ass.net \
--to=peterz@infradead.org \
--cc=changcheng.liu@intel.com \
--cc=douly.fnst@cn.fujitsu.com \
--cc=hpa@zytor.com \
--cc=linux-kernel@vger.kernel.org \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox