From: Will Deacon <will.deacon@arm.com>
To: Marc Zyngier <marc.zyngier@arm.com>
Cc: Shanker Donthineni <shankerd@codeaurora.org>,
linux-kernel <linux-kernel@vger.kernel.org>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
Catalin Marinas <catalin.marinas@arm.com>,
kvmarm <kvmarm@lists.cs.columbia.edu>,
Christoffer Dall <cdall@kernel.org>,
Vikram Sethi <vikrams@codeaurora.org>,
Sean Campbell <scampbel@codeaurora.org>,
Thomas Speier <tspeier@codeaurora.org>
Subject: Re: [PATCH v2] arm64: KVM: Use SMCCC_ARCH_WORKAROUND_1 for Falkor BP hardening
Date: Tue, 20 Mar 2018 09:47:44 +0000 [thread overview]
Message-ID: <20180320094744.GA24986@arm.com> (raw)
In-Reply-To: <fed53181-db58-9f48-0c5b-7eebe9eb9b10@arm.com>
On Mon, Mar 19, 2018 at 06:30:16PM +0000, Marc Zyngier wrote:
> On 06/03/18 10:32, Marc Zyngier wrote:
> > On Mon, 05 Mar 2018 17:06:43 +0000,
> > Shanker Donthineni wrote:
> >>
> >> The function SMCCC_ARCH_WORKAROUND_1 was introduced as part of SMC
> >> V1.1 Calling Convention to mitigate CVE-2017-5715. This patch uses
> >> the standard call SMCCC_ARCH_WORKAROUND_1 for Falkor chips instead
> >> of Silicon provider service ID 0xC2001700.
> >>
> >> Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>
> >> ---
> >> Chnages since v1:
> >> - Trivial change in cpucaps.h (refresh after removing ARM64_HARDEN_BP_POST_GUEST_EXIT)
> >>
> >> arch/arm64/include/asm/cpucaps.h | 5 ++--
> >> arch/arm64/include/asm/kvm_asm.h | 2 --
> >> arch/arm64/kernel/bpi.S | 8 ------
> >> arch/arm64/kernel/cpu_errata.c | 55 ++++++++++++++--------------------------
> >> arch/arm64/kvm/hyp/entry.S | 12 ---------
> >> arch/arm64/kvm/hyp/switch.c | 10 --------
> >> 6 files changed, 21 insertions(+), 71 deletions(-)
> >
> > Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
> >
> > Will/Catalin, if you want to take it via the arm64 tree, that's fine
> > by me.
>
> Please allow me to change my mind. This is going to conflict horribly
> with the VHE rework and the HYP randomization patches.
>
> I'll take it via the KVM tree, which will make everyone's life a lot easier.
Sure; if you need it:
Acked-by: Will Deacon <will.deacon@arm.com>
You'll probably want to comment out the ARM64_HARDEN_BP_POST_GUEST_EXIT
capability for now to avoid silly conflicts in -next. I can remove and
renumber at -rc1.
Will
next prev parent reply other threads:[~2018-03-20 9:47 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-05 17:06 [PATCH v2] arm64: KVM: Use SMCCC_ARCH_WORKAROUND_1 for Falkor BP hardening Shanker Donthineni
2018-03-06 10:32 ` Marc Zyngier
2018-03-19 18:30 ` Marc Zyngier
2018-03-20 9:47 ` Will Deacon [this message]
2018-03-09 13:48 ` Will Deacon
2018-03-10 18:40 ` Shanker Donthineni
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20180320094744.GA24986@arm.com \
--to=will.deacon@arm.com \
--cc=catalin.marinas@arm.com \
--cc=cdall@kernel.org \
--cc=kvmarm@lists.cs.columbia.edu \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=marc.zyngier@arm.com \
--cc=scampbel@codeaurora.org \
--cc=shankerd@codeaurora.org \
--cc=tspeier@codeaurora.org \
--cc=vikrams@codeaurora.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).