From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752180AbeCWVWd (ORCPT ); Fri, 23 Mar 2018 17:22:33 -0400 Received: from mail.bootlin.com ([62.4.15.54]:36263 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751691AbeCWVWc (ORCPT ); Fri, 23 Mar 2018 17:22:32 -0400 Date: Fri, 23 Mar 2018 22:22:30 +0100 From: Alexandre Belloni To: Florian Fainelli Cc: "David S . Miller" , Allan Nielsen , razvan.stefanescu@nxp.com, po.liu@nxp.com, Thomas Petazzoni , Andrew Lunn , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, James Hogan Subject: Re: [PATCH net-next 6/8] MIPS: mscc: Add switch to ocelot Message-ID: <20180323212230.GA12808@piout.net> References: <20180323201117.8416-1-alexandre.belloni@bootlin.com> <20180323201117.8416-7-alexandre.belloni@bootlin.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 23/03/2018 at 14:17:48 -0700, Florian Fainelli wrote: > On 03/23/2018 01:11 PM, Alexandre Belloni wrote: > > + > > + phy0: ethernet-phy@0 { > > + reg = <0>; > > + }; > > + phy1: ethernet-phy@1 { > > + reg = <1>; > > + }; > > + phy2: ethernet-phy@2 { > > + reg = <2>; > > + }; > > + phy3: ethernet-phy@3 { > > + reg = <3>; > > + }; > > These PHYs should be defined at the board DTS level. Those are internal PHYs, present on the SoC, I doubt anyone will have anything different while using the same SoC. -- Alexandre Belloni, Bootlin (formerly Free Electrons) Embedded Linux and Kernel engineering https://bootlin.com