[GIT PULL 0/8] perf/core improvements and fixes

[GIT PULL 0/8] perf/core improvements and fixes

[Arnaldo Carvalho de Melo]

Hi Ingo,

	Please consider pulling,

- Arnaldo

The following changes since commit 7a4ec938857cf534270b23545495300fbac7f5de:

  perf tools: Allow user to indicate path to objdump in command line (2012-09-05 19:41:55 -0300)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux tags/perf-core-for-mingo

for you to fetch changes up to 275ef3878f698941353780440fec6926107a320b:

  perf tools: Fix cache event name generation (2012-09-06 15:01:08 -0300)

----------------------------------------------------------------
perf/core improvements and fixes

. Fix hardware cache event name generation, fix from Jiri Olsa

. Add round trip test for sw, hw and cache event names, catching the
  problem Jiri fixed, after Jiri's patch, the test passes successfully.

. Clean target should do clean for lib/traceevent too, fix from David Ahern

. Check the right variable for allocation failure, fix from Namhyung Kim

. Set up evsel->tp_format regardless of evsel->name being set already,
  fix from Namhyung Kim

Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>

----------------------------------------------------------------
Arnaldo Carvalho de Melo (4):
      perf test: Add round trip test for sw and hw event names
      perf tools: Remove extraneous newline when parsing hardware cache events
      perf evlist: Add fprintf method
      perf test: Add roundtrip test for hardware cache events

David Ahern (1):
      perf tools: Clean target should do clean for lib/traceevent too

Jiri Olsa (1):
      perf tools: Fix cache event name generation

Namhyung Kim (2):
      perf header: Fix a typo on evsel
      perf header: Prepare tracepoint events regardless of name

 tools/perf/Makefile            |    5 +-
 tools/perf/builtin-test.c      |  114 ++++++++++++++++++++++++++++++++++++++++
 tools/perf/util/evlist.c       |   13 +++++
 tools/perf/util/evlist.h       |    2 +
 tools/perf/util/evsel.c        |    6 +--
 tools/perf/util/evsel.h        |    6 ++-
 tools/perf/util/header.c       |   36 ++++++++-----
 tools/perf/util/parse-events.c |    2 +-
 8 files changed, 163 insertions(+), 21 deletions(-)

Re: [GIT PULL 0/8] perf/core improvements and fixes

[Ingo Molnar]

* Arnaldo Carvalho de Melo <acme@infradead.org> wrote:

> Hi Ingo,
> 
> 	Please consider pulling,
> 
> - Arnaldo
> 
> The following changes since commit 7a4ec938857cf534270b23545495300fbac7f5de:
> 
>   perf tools: Allow user to indicate path to objdump in command line (2012-09-05 19:41:55 -0300)
> 
> are available in the git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux tags/perf-core-for-mingo
> 
> for you to fetch changes up to 275ef3878f698941353780440fec6926107a320b:
> 
>   perf tools: Fix cache event name generation (2012-09-06 15:01:08 -0300)
> 
> ----------------------------------------------------------------
> perf/core improvements and fixes
> 
> . Fix hardware cache event name generation, fix from Jiri Olsa
> 
> . Add round trip test for sw, hw and cache event names, catching the
>   problem Jiri fixed, after Jiri's patch, the test passes successfully.
> 
> . Clean target should do clean for lib/traceevent too, fix from David Ahern
> 
> . Check the right variable for allocation failure, fix from Namhyung Kim
> 
> . Set up evsel->tp_format regardless of evsel->name being set already,
>   fix from Namhyung Kim
> 
> Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> 
> ----------------------------------------------------------------
> Arnaldo Carvalho de Melo (4):
>       perf test: Add round trip test for sw and hw event names
>       perf tools: Remove extraneous newline when parsing hardware cache events
>       perf evlist: Add fprintf method
>       perf test: Add roundtrip test for hardware cache events
> 
> David Ahern (1):
>       perf tools: Clean target should do clean for lib/traceevent too
> 
> Jiri Olsa (1):
>       perf tools: Fix cache event name generation
> 
> Namhyung Kim (2):
>       perf header: Fix a typo on evsel
>       perf header: Prepare tracepoint events regardless of name
> 
>  tools/perf/Makefile            |    5 +-
>  tools/perf/builtin-test.c      |  114 ++++++++++++++++++++++++++++++++++++++++
>  tools/perf/util/evlist.c       |   13 +++++
>  tools/perf/util/evlist.h       |    2 +
>  tools/perf/util/evsel.c        |    6 +--
>  tools/perf/util/evsel.h        |    6 ++-
>  tools/perf/util/header.c       |   36 ++++++++-----
>  tools/perf/util/parse-events.c |    2 +-
>  8 files changed, 163 insertions(+), 21 deletions(-)

Pulled, thanks a lot Arnaldo!

	Ingo

[GIT PULL 0/8] perf/core improvements and fixes

[Jiri Olsa]

hi Ingo,
please consider pulling

thanks,
jirka


The following changes since commit 26f273802b6ed28e059f4359bc7711dffceda022:

  Merge tag 'perf-core-for-mingo' of git://git.kernel.org/pub/scm/linux/kernel/git/jolsa/perf into perf/core (2014-05-12 17:57:48 +0200)

are available in the git repository at:


  git://git.kernel.org/pub/scm/linux/kernel/git/jolsa/perf.git tags/perf-core-for-mingo

for you to fetch changes up to 97eac381b113932bd7bd4a5c3c68b18e9ff7a2a0:

  perf tools: Add libdw DWARF post unwind support for ARM (2014-05-16 11:39:29 +0200)

----------------------------------------------------------------
perf/core improvements and fixes:

. Add libdw DWARF post unwind support for ARM (Jean Pihet)

. Consolidate types.h for ARM and ARM64 (Jean Pihet)

. Fix possible null pointer dereference in session.c (Masanari Iida)

. Cleanup, remove unused variables in map_switch_event() (Dongsheng Yang)

. Remove nr_state_machine_bugs in perf latency (Dongsheng Yang)

. Remove usage of trace_sched_wakeup(.success) (Peter Zijlstra)

Signed-off-by: Jiri Olsa <jolsa@kernel.org>

----------------------------------------------------------------
Dongsheng Yang (2):
      perf sched: Remove nr_state_machine_bugs in perf latency
      perf sched: Cleanup, remove unused variables in map_switch_event()

Jean Pihet (4):
      perf tools: Consolidate types.h for ARM and ARM64
      perf tests: Introduce perf_regs_load function on ARM
      perf tests: Add dwarf unwind test on ARM
      perf tools: Add libdw DWARF post unwind support for ARM

Masanari Iida (1):
      perf session: Fix possible null pointer dereference in session.c

Peter Zijlstra (1):
      perf tools: Remove usage of trace_sched_wakeup(.success)

 tools/perf/Makefile.perf                  |  2 +-
 tools/perf/arch/arm/Makefile              |  7 ++++
 tools/perf/arch/arm/include/perf_regs.h   |  7 +++-
 tools/perf/arch/arm/tests/dwarf-unwind.c  | 60 +++++++++++++++++++++++++++++++
 tools/perf/arch/arm/tests/regs_load.S     | 58 ++++++++++++++++++++++++++++++
 tools/perf/arch/arm/util/unwind-libdw.c   | 36 +++++++++++++++++++
 tools/perf/arch/arm64/include/perf_regs.h |  2 +-
 tools/perf/builtin-sched.c                | 32 ++++++-----------
 tools/perf/config/Makefile                |  4 +--
 tools/perf/tests/builtin-test.c           |  2 +-
 tools/perf/tests/evsel-tp-sched.c         |  3 --
 tools/perf/tests/tests.h                  |  2 +-
 tools/perf/util/session.c                 |  5 +--
 13 files changed, 187 insertions(+), 33 deletions(-)
 create mode 100644 tools/perf/arch/arm/tests/dwarf-unwind.c
 create mode 100644 tools/perf/arch/arm/tests/regs_load.S
 create mode 100644 tools/perf/arch/arm/util/unwind-libdw.c

Re: [GIT PULL 0/8] perf/core improvements and fixes

[Ingo Molnar]

* Jiri Olsa <jolsa@kernel.org> wrote:

> hi Ingo,
> please consider pulling
> 
> thanks,
> jirka
> 
> 
> The following changes since commit 26f273802b6ed28e059f4359bc7711dffceda022:
> 
>   Merge tag 'perf-core-for-mingo' of git://git.kernel.org/pub/scm/linux/kernel/git/jolsa/perf into perf/core (2014-05-12 17:57:48 +0200)
> 
> are available in the git repository at:
> 
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/jolsa/perf.git tags/perf-core-for-mingo
> 
> for you to fetch changes up to 97eac381b113932bd7bd4a5c3c68b18e9ff7a2a0:
> 
>   perf tools: Add libdw DWARF post unwind support for ARM (2014-05-16 11:39:29 +0200)
> 
> ----------------------------------------------------------------
> perf/core improvements and fixes:
> 
> . Add libdw DWARF post unwind support for ARM (Jean Pihet)
> 
> . Consolidate types.h for ARM and ARM64 (Jean Pihet)
> 
> . Fix possible null pointer dereference in session.c (Masanari Iida)
> 
> . Cleanup, remove unused variables in map_switch_event() (Dongsheng Yang)
> 
> . Remove nr_state_machine_bugs in perf latency (Dongsheng Yang)
> 
> . Remove usage of trace_sched_wakeup(.success) (Peter Zijlstra)
> 
> Signed-off-by: Jiri Olsa <jolsa@kernel.org>
> 
> ----------------------------------------------------------------
> Dongsheng Yang (2):
>       perf sched: Remove nr_state_machine_bugs in perf latency
>       perf sched: Cleanup, remove unused variables in map_switch_event()
> 
> Jean Pihet (4):
>       perf tools: Consolidate types.h for ARM and ARM64
>       perf tests: Introduce perf_regs_load function on ARM
>       perf tests: Add dwarf unwind test on ARM
>       perf tools: Add libdw DWARF post unwind support for ARM
> 
> Masanari Iida (1):
>       perf session: Fix possible null pointer dereference in session.c
> 
> Peter Zijlstra (1):
>       perf tools: Remove usage of trace_sched_wakeup(.success)
> 
>  tools/perf/Makefile.perf                  |  2 +-
>  tools/perf/arch/arm/Makefile              |  7 ++++
>  tools/perf/arch/arm/include/perf_regs.h   |  7 +++-
>  tools/perf/arch/arm/tests/dwarf-unwind.c  | 60 +++++++++++++++++++++++++++++++
>  tools/perf/arch/arm/tests/regs_load.S     | 58 ++++++++++++++++++++++++++++++
>  tools/perf/arch/arm/util/unwind-libdw.c   | 36 +++++++++++++++++++
>  tools/perf/arch/arm64/include/perf_regs.h |  2 +-
>  tools/perf/builtin-sched.c                | 32 ++++++-----------
>  tools/perf/config/Makefile                |  4 +--
>  tools/perf/tests/builtin-test.c           |  2 +-
>  tools/perf/tests/evsel-tp-sched.c         |  3 --
>  tools/perf/tests/tests.h                  |  2 +-
>  tools/perf/util/session.c                 |  5 +--
>  13 files changed, 187 insertions(+), 33 deletions(-)
>  create mode 100644 tools/perf/arch/arm/tests/dwarf-unwind.c
>  create mode 100644 tools/perf/arch/arm/tests/regs_load.S
>  create mode 100644 tools/perf/arch/arm/util/unwind-libdw.c

Pulled, thanks a lot Jiri!

	Ingo

[GIT PULL 0/8] perf/core improvements and fixes

[Arnaldo Carvalho de Melo]

Hi Ingo,

	Please consider pulling,

Best Regards,

- Arnaldo

The following changes since commit 07394b5f13a04f86b27e0ddd96a36c7d9bfe1a4f:

  Merge tag 'perf-core-for-mingo' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/core (2014-09-27 09:15:48 +0200)

are available in the git repository at:


  git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git tags/perf-core-for-mingo

for you to fetch changes up to 281f92f233a59ef52bb45287242bd815a67f5647:

  perf record: Fix error message for --filter option not coming after tracepoint (2014-10-01 15:05:32 -0300)

----------------------------------------------------------------
perf/core improvements and fixes:

User visible:

. Fix mmap return address truncation to 32-bit in 'perf trace'. (Chang Hyun Park)

o Support operations for shared futexes. (Davidlohr Bueso)

. Fix error message for --filter option not coming after tracepoint. (Arnaldo Carvalho de Melo)

Infrastructure:

. Refactor unit and scale function parameters for pmu parsing routines. (Matt Fleming)

. Improve DSO long names lookup with rbtree, resulting in great speedup for
  workloads with lots of DSOs. (Waiman Long)

. Fix build breakage on arm64 targets. (Will Deacon)

Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>

----------------------------------------------------------------
Arnaldo Carvalho de Melo (1):
      perf record: Fix error message for --filter option not coming after tracepoint

Chang Hyun Park (1):
      perf trace: Fix mmap return address truncation to 32-bit

Davidlohr Bueso (2):
      perf bench futex: Support operations for shared futexes
      perf bench futex: Sanitize -q option in requeue

Matt Fleming (1):
      perf tools: Refactor unit and scale function parameters

Waiman Long (2):
      perf symbols: Encapsulate dsos list head into struct dsos
      perf symbols: Improve DSO long names lookup speed with rbtree

Will Deacon (1):
      perf tools: Fix build breakage on arm64 targets

 tools/perf/arch/arm64/util/unwind-libunwind.c |  1 +
 tools/perf/bench/futex-hash.c                 |  7 ++-
 tools/perf/bench/futex-requeue.c              | 28 +++++----
 tools/perf/bench/futex-wake.c                 | 15 +++--
 tools/perf/builtin-trace.c                    |  6 +-
 tools/perf/util/dso.c                         | 85 +++++++++++++++++++++++----
 tools/perf/util/dso.h                         | 16 ++++-
 tools/perf/util/header.c                      | 32 +++++-----
 tools/perf/util/machine.c                     | 25 ++++----
 tools/perf/util/machine.h                     |  5 +-
 tools/perf/util/parse-events.c                | 11 ++--
 tools/perf/util/pmu.c                         | 38 +++++++-----
 tools/perf/util/pmu.h                         |  7 ++-
 tools/perf/util/probe-event.c                 |  3 +-
 tools/perf/util/symbol-elf.c                  |  7 ++-
 15 files changed, 200 insertions(+), 86 deletions(-)

Re: [GIT PULL 0/8] perf/core improvements and fixes

[Ingo Molnar]

* Arnaldo Carvalho de Melo <acme@kernel.org> wrote:

> Hi Ingo,
> 
> 	Please consider pulling,
> 
> Best Regards,
> 
> - Arnaldo
> 
> The following changes since commit 07394b5f13a04f86b27e0ddd96a36c7d9bfe1a4f:
> 
>   Merge tag 'perf-core-for-mingo' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/core (2014-09-27 09:15:48 +0200)
> 
> are available in the git repository at:
> 
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git tags/perf-core-for-mingo
> 
> for you to fetch changes up to 281f92f233a59ef52bb45287242bd815a67f5647:
> 
>   perf record: Fix error message for --filter option not coming after tracepoint (2014-10-01 15:05:32 -0300)
> 
> ----------------------------------------------------------------
> perf/core improvements and fixes:
> 
> User visible:
> 
> . Fix mmap return address truncation to 32-bit in 'perf trace'. (Chang Hyun Park)
> 
> o Support operations for shared futexes. (Davidlohr Bueso)
> 
> . Fix error message for --filter option not coming after tracepoint. (Arnaldo Carvalho de Melo)
> 
> Infrastructure:
> 
> . Refactor unit and scale function parameters for pmu parsing routines. (Matt Fleming)
> 
> . Improve DSO long names lookup with rbtree, resulting in great speedup for
>   workloads with lots of DSOs. (Waiman Long)
> 
> . Fix build breakage on arm64 targets. (Will Deacon)
> 
> Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> 
> ----------------------------------------------------------------
> Arnaldo Carvalho de Melo (1):
>       perf record: Fix error message for --filter option not coming after tracepoint
> 
> Chang Hyun Park (1):
>       perf trace: Fix mmap return address truncation to 32-bit
> 
> Davidlohr Bueso (2):
>       perf bench futex: Support operations for shared futexes
>       perf bench futex: Sanitize -q option in requeue
> 
> Matt Fleming (1):
>       perf tools: Refactor unit and scale function parameters
> 
> Waiman Long (2):
>       perf symbols: Encapsulate dsos list head into struct dsos
>       perf symbols: Improve DSO long names lookup speed with rbtree
> 
> Will Deacon (1):
>       perf tools: Fix build breakage on arm64 targets
> 
>  tools/perf/arch/arm64/util/unwind-libunwind.c |  1 +
>  tools/perf/bench/futex-hash.c                 |  7 ++-
>  tools/perf/bench/futex-requeue.c              | 28 +++++----
>  tools/perf/bench/futex-wake.c                 | 15 +++--
>  tools/perf/builtin-trace.c                    |  6 +-
>  tools/perf/util/dso.c                         | 85 +++++++++++++++++++++++----
>  tools/perf/util/dso.h                         | 16 ++++-
>  tools/perf/util/header.c                      | 32 +++++-----
>  tools/perf/util/machine.c                     | 25 ++++----
>  tools/perf/util/machine.h                     |  5 +-
>  tools/perf/util/parse-events.c                | 11 ++--
>  tools/perf/util/pmu.c                         | 38 +++++++-----
>  tools/perf/util/pmu.h                         |  7 ++-
>  tools/perf/util/probe-event.c                 |  3 +-
>  tools/perf/util/symbol-elf.c                  |  7 ++-
>  15 files changed, 200 insertions(+), 86 deletions(-)

Pulled into tip:perf/core, thanks a lot Arnaldo!

	Ingo

[GIT PULL 0/8] perf/core improvements and fixes

[Arnaldo Carvalho de Melo]

Hi Ingo,

	Please consider pulling, this is on top of perf-core-for-mingo, that is
still outstanding,

Thanks!

- Arnaldo

The following changes since commit b031220d520238075bd99513a420e65cf37866ad:

  perf probe: Fix to return error if no probe is added (2015-06-16 11:39:51 -0300)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git tags/perf-core-for-mingo-2

for you to fetch changes up to 5d484f99aed547e235f2229653c95392a1bc3692:

  perf top: Allow disabling/enabling events dynamicly (2015-06-17 16:50:52 -0300)

----------------------------------------------------------------
perf/core improvements and fixes:

User visible:

- Allow disabling/enabling events dynamicly in 'perf top':
  a 'perf top' session can instantly become a 'perf report'
  one, i.e. going from dynamic analysis to a static one,
  returning to a dynamic one is possible, to toogle the
  modes, just press CTRL+z. (Arnaldo Carvalho de Melo)

- Greatly speed up 'perf probe --list' by caching debuginfo
  (Masami Hiramatsu)

- Fix 'perf trace' race condition at the end of started
  workloads (Sukadev Bhattiprolu)

- Fix a problem when opening old perf.data with different
  byte order (Wang Nan)

Infrastructure:

- Ignore .config-detected in .gitignore (Wang Nan)

- Move libtraceevent dynamic list to separated LDFLAGS
  variable (Wang Nan)

Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>

----------------------------------------------------------------
Arnaldo Carvalho de Melo (2):
      perf evlist: Add toggle_enable() method
      perf top: Allow disabling/enabling events dynamicly

Masami Hiramatsu (2):
      perf probe: Show usage even if the last event is skipped
      perf probe: Speed up perf probe --list by caching debuginfo

Sukadev Bhattiprolu (1):
      perf trace: Fix race condition at the end of started workloads

Wang Nan (3):
      perf tools: Ignore .config-detected in .gitignore
      perf tools: Fix a problem when opening old perf.data with different byte order
      perf tools: Move libtraceevent dynamic list to separated LDFLAGS variable

 tools/perf/.gitignore          |  1 +
 tools/perf/Makefile.perf       |  8 ++--
 tools/perf/builtin-top.c       | 52 ++++++++++++++++++--------
 tools/perf/ui/browsers/hists.c |  2 +
 tools/perf/util/evlist.c       | 18 ++++++++-
 tools/perf/util/evlist.h       |  2 +
 tools/perf/util/probe-event.c  | 83 +++++++++++++++++++++++++++++++-----------
 tools/perf/util/session.c      | 50 ++++++++++++++++++-------
 8 files changed, 160 insertions(+), 56 deletions(-)

Re: [GIT PULL 0/8] perf/core improvements and fixes

[Ingo Molnar]

* Arnaldo Carvalho de Melo <acme@kernel.org> wrote:

> Hi Ingo,
> 
> 	Please consider pulling, this is on top of perf-core-for-mingo, that is
> still outstanding,
> 
> Thanks!
> 
> - Arnaldo
> 
> The following changes since commit b031220d520238075bd99513a420e65cf37866ad:
> 
>   perf probe: Fix to return error if no probe is added (2015-06-16 11:39:51 -0300)
> 
> are available in the git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git tags/perf-core-for-mingo-2
> 
> for you to fetch changes up to 5d484f99aed547e235f2229653c95392a1bc3692:
> 
>   perf top: Allow disabling/enabling events dynamicly (2015-06-17 16:50:52 -0300)
> 
> ----------------------------------------------------------------
> perf/core improvements and fixes:
> 
> User visible:
> 
> - Allow disabling/enabling events dynamicly in 'perf top':
>   a 'perf top' session can instantly become a 'perf report'
>   one, i.e. going from dynamic analysis to a static one,
>   returning to a dynamic one is possible, to toogle the
>   modes, just press CTRL+z. (Arnaldo Carvalho de Melo)

Nice!! :-)

Btw., it would be nice if the status line carried information about whether 
collection is 'frozen' or running, at a glance. A hint might also suggest how to 
unfreeze the session - in case someone pressed Ctrl-Z to suspend the perf top 
session ...

Also, there's now a GUI inconsistency with perf report: which will now exit on 
Ctrl-Z. It should probably print a warning in the status line instead, that 
freezing/unfreezing only works in 'perf top'.

> 
> - Greatly speed up 'perf probe --list' by caching debuginfo
>   (Masami Hiramatsu)
> 
> - Fix 'perf trace' race condition at the end of started
>   workloads (Sukadev Bhattiprolu)
> 
> - Fix a problem when opening old perf.data with different
>   byte order (Wang Nan)
> 
> Infrastructure:
> 
> - Ignore .config-detected in .gitignore (Wang Nan)
> 
> - Move libtraceevent dynamic list to separated LDFLAGS
>   variable (Wang Nan)
> 
> Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> 
> ----------------------------------------------------------------
> Arnaldo Carvalho de Melo (2):
>       perf evlist: Add toggle_enable() method
>       perf top: Allow disabling/enabling events dynamicly
> 
> Masami Hiramatsu (2):
>       perf probe: Show usage even if the last event is skipped
>       perf probe: Speed up perf probe --list by caching debuginfo
> 
> Sukadev Bhattiprolu (1):
>       perf trace: Fix race condition at the end of started workloads
> 
> Wang Nan (3):
>       perf tools: Ignore .config-detected in .gitignore
>       perf tools: Fix a problem when opening old perf.data with different byte order
>       perf tools: Move libtraceevent dynamic list to separated LDFLAGS variable
> 
>  tools/perf/.gitignore          |  1 +
>  tools/perf/Makefile.perf       |  8 ++--
>  tools/perf/builtin-top.c       | 52 ++++++++++++++++++--------
>  tools/perf/ui/browsers/hists.c |  2 +
>  tools/perf/util/evlist.c       | 18 ++++++++-
>  tools/perf/util/evlist.h       |  2 +
>  tools/perf/util/probe-event.c  | 83 +++++++++++++++++++++++++++++++-----------
>  tools/perf/util/session.c      | 50 ++++++++++++++++++-------
>  8 files changed, 160 insertions(+), 56 deletions(-)

Pulled, thanks a lot Arnaldo!

	Ingo

[GIT PULL 0/8] perf/core improvements and fixes

[Arnaldo Carvalho de Melo]

Hi Ingo,

	Please consider pulling,

- Arnaldo

The following changes since commit 9059b284caecb628fac826c2c5cc8ee85708eec1:

  Merge tag 'perf-core-for-mingo-2' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/core (2015-09-15 08:50:59 +0200)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git tags/perf-core-for-mingo

for you to fetch changes up to bbbe6bf6037d77816c4a19aaf35f4cecf662b49a:

  perf tools: Introduce regs_query_register_offset() for x86 (2015-09-15 09:48:33 -0300)

----------------------------------------------------------------
perf/core improvements and fixes:

User visible:

- Enhance the error reporting of tracepoint event parsing, e.g.:

    $ oldperf record -e sched:sched_switc usleep 1
    event syntax error: 'sched:sched_switc'
                        \___ unknown tracepoint
    Run 'perf list' for a list of valid events

  Now we get the much nicer:

    $ perf record -e sched:sched_switc ls
    event syntax error: 'sched:sched_switc'
                         \___ can't access trace events

    Error: No permissions to read /sys/kernel/debug/tracing/events/sched/sched_switc
    Hint:  Try 'sudo mount -o remount,mode=755 /sys/kernel/debug'

  And after we have those mount point permissions fixed:

    $ perf record -e sched:sched_switc ls
    event syntax error: 'sched:sched_switc'
                         \___ unknown tracepoint

    Error: File /sys/kernel/debug/tracing/events/sched/sched_switc not found.
    Hint:  Perhaps this kernel misses some CONFIG_ setting to enable this feature?.

  Now its just a matter of using what git uses to suggest alternatives when we
  make a typo, i.e. that it is just an 'h' missing :-)

  I.e. basically now the event parsing routing uses the strerror_open()
  routines introduced by and used in 'perf trace' work. (Jiri Olsa)

Infrastructure:

- Export init/exit_probe_symbol_maps() from 'perf probe' for use in eBPF
  (Namhyung Kim)

- Free perf_probe_event in cleanup_perf_probe_events() (Namhyung Kim)

- regs_query_register_offset() infrastructure + implementation for x86.
  First user will be the perf/eBPF code (Wang Nan)

Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>

----------------------------------------------------------------
Jiri Olsa (4):
      tools: Add err.h with ERR_PTR PTR_ERR interface
      perf tools: Propagate error info for the tracepoint parsing
      perf evsel: Propagate error info from tp_format
      perf tools: Enhance parsing events tracepoint error output

Namhyung Kim (2):
      perf probe: Free perf_probe_event in cleanup_perf_probe_events()
      perf probe: Export init/exit_probe_symbol_maps()

Wang Nan (2):
      perf tools: regs_query_register_offset() infrastructure
      perf tools: Introduce regs_query_register_offset() for x86

 tools/include/linux/err.h                   |  49 +++++++++++
 tools/perf/arch/x86/Makefile                |   1 +
 tools/perf/arch/x86/util/dwarf-regs.c       | 122 ++++++++++++++++++++--------
 tools/perf/builtin-probe.c                  |   5 ++
 tools/perf/builtin-trace.c                  |  19 +++--
 tools/perf/config/Makefile                  |   4 +
 tools/perf/tests/evsel-tp-sched.c           |  10 ++-
 tools/perf/tests/mmap-basic.c               |   3 +-
 tools/perf/tests/openat-syscall-all-cpus.c  |   3 +-
 tools/perf/tests/openat-syscall-tp-fields.c |   3 +-
 tools/perf/tests/openat-syscall.c           |   3 +-
 tools/perf/util/evlist.c                    |   3 +-
 tools/perf/util/evsel.c                     |  16 +++-
 tools/perf/util/evsel.h                     |   3 +
 tools/perf/util/include/dwarf-regs.h        |   8 ++
 tools/perf/util/parse-events.c              |  66 +++++++++++----
 tools/perf/util/parse-events.h              |   3 +-
 tools/perf/util/parse-events.y              |  16 ++--
 tools/perf/util/probe-event.c               |  32 ++++----
 tools/perf/util/probe-event.h               |   2 +
 tools/perf/util/trace-event.c               |  15 +++-
 21 files changed, 291 insertions(+), 95 deletions(-)
 create mode 100644 tools/include/linux/err.h

Re: [GIT PULL 0/8] perf/core improvements and fixes

[Ingo Molnar]

* Arnaldo Carvalho de Melo <acme@kernel.org> wrote:

> Hi Ingo,
> 
> 	Please consider pulling,
> 
> - Arnaldo
> 
> The following changes since commit 9059b284caecb628fac826c2c5cc8ee85708eec1:
> 
>   Merge tag 'perf-core-for-mingo-2' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/core (2015-09-15 08:50:59 +0200)
> 
> are available in the git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git tags/perf-core-for-mingo

So your perf/urgent bits now conflict with the latest perf/core, in 
tools/perf/ui/browsers/hists.c. I have merged perf/urgent into perf/core - please 
double check my resolution (d71b0ad8d309).

> 
> for you to fetch changes up to bbbe6bf6037d77816c4a19aaf35f4cecf662b49a:
> 
>   perf tools: Introduce regs_query_register_offset() for x86 (2015-09-15 09:48:33 -0300)
> 
> ----------------------------------------------------------------
> perf/core improvements and fixes:
> 
> User visible:
> 
> - Enhance the error reporting of tracepoint event parsing, e.g.:
> 
>     $ oldperf record -e sched:sched_switc usleep 1
>     event syntax error: 'sched:sched_switc'
>                         \___ unknown tracepoint
>     Run 'perf list' for a list of valid events
> 
>   Now we get the much nicer:
> 
>     $ perf record -e sched:sched_switc ls
>     event syntax error: 'sched:sched_switc'
>                          \___ can't access trace events
> 
>     Error: No permissions to read /sys/kernel/debug/tracing/events/sched/sched_switc
>     Hint:  Try 'sudo mount -o remount,mode=755 /sys/kernel/debug'
> 
>   And after we have those mount point permissions fixed:
> 
>     $ perf record -e sched:sched_switc ls
>     event syntax error: 'sched:sched_switc'
>                          \___ unknown tracepoint
> 
>     Error: File /sys/kernel/debug/tracing/events/sched/sched_switc not found.
>     Hint:  Perhaps this kernel misses some CONFIG_ setting to enable this feature?.
> 
>   Now its just a matter of using what git uses to suggest alternatives when we
>   make a typo, i.e. that it is just an 'h' missing :-)

Nice changes!

Btw., wouldn't it be even better to allow partial matches? Not allowing 
'sched:sched_switc' is unnecessarily pedantic IMHO.

For example 'perf list' allows partial matches as well. As long as the resulting 
event is unique, we should allow partial matches. If it's not unique, we should 
print the first 3 matching entries or so.

There's a real UI advantage as well: I could abbreviate the command line with:

  -e sched_sw

instead of always being forced to type out the full tracepoint name.

(Programmatic tracepoint usage and portable scripts should naturally always spell 
out the full event, to make sure new tracepoints don't cause overlaps - but ad-hoc 
usage can do abbreviations just fine.)


>   I.e. basically now the event parsing routing uses the strerror_open()
>   routines introduced by and used in 'perf trace' work. (Jiri Olsa)
> 
> Infrastructure:
> 
> - Export init/exit_probe_symbol_maps() from 'perf probe' for use in eBPF
>   (Namhyung Kim)
> 
> - Free perf_probe_event in cleanup_perf_probe_events() (Namhyung Kim)
> 
> - regs_query_register_offset() infrastructure + implementation for x86.
>   First user will be the perf/eBPF code (Wang Nan)
> 
> Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> 
> ----------------------------------------------------------------
> Jiri Olsa (4):
>       tools: Add err.h with ERR_PTR PTR_ERR interface
>       perf tools: Propagate error info for the tracepoint parsing
>       perf evsel: Propagate error info from tp_format
>       perf tools: Enhance parsing events tracepoint error output
> 
> Namhyung Kim (2):
>       perf probe: Free perf_probe_event in cleanup_perf_probe_events()
>       perf probe: Export init/exit_probe_symbol_maps()
> 
> Wang Nan (2):
>       perf tools: regs_query_register_offset() infrastructure
>       perf tools: Introduce regs_query_register_offset() for x86
> 
>  tools/include/linux/err.h                   |  49 +++++++++++
>  tools/perf/arch/x86/Makefile                |   1 +
>  tools/perf/arch/x86/util/dwarf-regs.c       | 122 ++++++++++++++++++++--------
>  tools/perf/builtin-probe.c                  |   5 ++
>  tools/perf/builtin-trace.c                  |  19 +++--
>  tools/perf/config/Makefile                  |   4 +
>  tools/perf/tests/evsel-tp-sched.c           |  10 ++-
>  tools/perf/tests/mmap-basic.c               |   3 +-
>  tools/perf/tests/openat-syscall-all-cpus.c  |   3 +-
>  tools/perf/tests/openat-syscall-tp-fields.c |   3 +-
>  tools/perf/tests/openat-syscall.c           |   3 +-
>  tools/perf/util/evlist.c                    |   3 +-
>  tools/perf/util/evsel.c                     |  16 +++-
>  tools/perf/util/evsel.h                     |   3 +
>  tools/perf/util/include/dwarf-regs.h        |   8 ++
>  tools/perf/util/parse-events.c              |  66 +++++++++++----
>  tools/perf/util/parse-events.h              |   3 +-
>  tools/perf/util/parse-events.y              |  16 ++--
>  tools/perf/util/probe-event.c               |  32 ++++----
>  tools/perf/util/probe-event.h               |   2 +
>  tools/perf/util/trace-event.c               |  15 +++-
>  21 files changed, 291 insertions(+), 95 deletions(-)
>  create mode 100644 tools/include/linux/err.h

Pulled, thanks a lot Arnaldo!

	Ingo

Re: [GIT PULL 0/8] perf/core improvements and fixes

[Arnaldo Carvalho de Melo]

Em Wed, Sep 16, 2015 at 09:25:44AM +0200, Ingo Molnar escreveu:
> 
> * Arnaldo Carvalho de Melo <acme@kernel.org> wrote:
> 
> > Hi Ingo,
> > 
> > 	Please consider pulling,
> > 
> > - Arnaldo
> > 
> > The following changes since commit 9059b284caecb628fac826c2c5cc8ee85708eec1:
> > 
> >   Merge tag 'perf-core-for-mingo-2' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/core (2015-09-15 08:50:59 +0200)
> > 
> > are available in the git repository at:
> > 
> >   git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git tags/perf-core-for-mingo
> 
> So your perf/urgent bits now conflict with the latest perf/core, in 
> tools/perf/ui/browsers/hists.c. I have merged perf/urgent into perf/core - please 
> double check my resolution (d71b0ad8d309).

Looks fine, tested it even, thanks!

- Arnaldo

[GIT PULL 0/8] perf/core improvements and fixes

[Arnaldo Carvalho de Melo]

Hi Ingo,

	Please consider pulling.

- Arnaldo

BTW.: There are several outstanding patchkits needing review and processing,
I'll be out this week for a conference, will try and speed up processing next
week.

The following changes since commit 0e537fef24d64f7bf3ef61a27edf64a8d9a5424c:

  Merge tag 'perf-core-for-mingo' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/core (2015-10-08 10:52:44 +0200)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git tags/perf-core-for-mingo

for you to fetch changes up to 3a70fcd3a4db56731f67f0189514953c74257944:

  tools build: Fix cross compile build (2015-10-13 11:59:43 -0300)

----------------------------------------------------------------
perf/core improvements and fixes:

User visible:

- Use the alternative with the most descriptive filename containing
  a vmlinux file for a given build-id, providing a better title line
  for tools such as 'annotate' (Arnaldo Carvalho de Melo)

- Remove help messages about previous right and left arrow keybidings, that
  were repurposed for horizontal scrolling (Arnaldo Carvalho de Melo)

- Inform how to reset the symbol filter in the hists browser (top & report)
  (Arnaldo Carvalho de Melo)

- Add 'm' key for context menu display in the hists browser, that became
  inacessible with the repurposing of the right arrow key for horizontal
  scrolling (Namhyung Kim)

- Use debug_frame for callchains if eh_frame is unusable (Rabin Vicent)

Build fixes:

- Fix strict-aliasing breakage with gcc 4.4 in the READ_ONCE/WRITE_ONCE code
  adopted from the kernel tree, that builds with -fno-strict-aliasing while
  tools/perf/ uses -Wstrict-aliasing=3 (Jiri Olsa)

- Fix unw_word_t pointer casts in code using libunwind for callchains,
  fixing the build in at least 32-bit MIPS systems (Rabin Vicent)

- Workaround cross compile build problems related to fixdep (Jiri Olsa)

Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>

----------------------------------------------------------------
Arnaldo Carvalho de Melo (3):
      perf symbols: Try the .debug/ DSO cache as a last resort
      perf ui browsers: Remove help messages about use of right and arrow keys
      perf hists browser: Inform how to reset the symbol filter

Jiri Olsa (2):
      tools include: Fix strict-aliasing rules breakage
      tools build: Fix cross compile build

Namhyung Kim (1):
      perf hists browser: Add 'm' key for context menu display

Rabin Vincent (2):
      perf callchain: Use debug_frame if eh_frame is unusable
      perf callchains: Fix unw_word_t pointer casts

 tools/build/Makefile.include       |  4 ++++
 tools/include/linux/compiler.h     | 32 ++++++++++++++++++++++++--------
 tools/perf/ui/browsers/annotate.c  |  6 +++---
 tools/perf/ui/browsers/hists.c     | 13 ++++++++-----
 tools/perf/ui/browsers/map.c       |  2 +-
 tools/perf/ui/browsers/scripts.c   |  2 +-
 tools/perf/util/symbol.c           | 18 +++++++++---------
 tools/perf/util/unwind-libunwind.c | 14 ++++++++------
 8 files changed, 58 insertions(+), 33 deletions(-)

Re: [GIT PULL 0/8] perf/core improvements and fixes

[Ingo Molnar]

* Arnaldo Carvalho de Melo <acme@kernel.org> wrote:

> Hi Ingo,
> 
> 	Please consider pulling.
> 
> - Arnaldo
> 
> BTW.: There are several outstanding patchkits needing review and processing,
> I'll be out this week for a conference, will try and speed up processing next
> week.
> 
> The following changes since commit 0e537fef24d64f7bf3ef61a27edf64a8d9a5424c:
> 
>   Merge tag 'perf-core-for-mingo' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/core (2015-10-08 10:52:44 +0200)
> 
> are available in the git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git tags/perf-core-for-mingo
> 
> for you to fetch changes up to 3a70fcd3a4db56731f67f0189514953c74257944:
> 
>   tools build: Fix cross compile build (2015-10-13 11:59:43 -0300)
> 
> ----------------------------------------------------------------
> perf/core improvements and fixes:
> 
> User visible:
> 
> - Use the alternative with the most descriptive filename containing
>   a vmlinux file for a given build-id, providing a better title line
>   for tools such as 'annotate' (Arnaldo Carvalho de Melo)
> 
> - Remove help messages about previous right and left arrow keybidings, that
>   were repurposed for horizontal scrolling (Arnaldo Carvalho de Melo)
> 
> - Inform how to reset the symbol filter in the hists browser (top & report)
>   (Arnaldo Carvalho de Melo)
> 
> - Add 'm' key for context menu display in the hists browser, that became
>   inacessible with the repurposing of the right arrow key for horizontal
>   scrolling (Namhyung Kim)
> 
> - Use debug_frame for callchains if eh_frame is unusable (Rabin Vicent)
> 
> Build fixes:
> 
> - Fix strict-aliasing breakage with gcc 4.4 in the READ_ONCE/WRITE_ONCE code
>   adopted from the kernel tree, that builds with -fno-strict-aliasing while
>   tools/perf/ uses -Wstrict-aliasing=3 (Jiri Olsa)
> 
> - Fix unw_word_t pointer casts in code using libunwind for callchains,
>   fixing the build in at least 32-bit MIPS systems (Rabin Vicent)
> 
> - Workaround cross compile build problems related to fixdep (Jiri Olsa)
> 
> Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> 
> ----------------------------------------------------------------
> Arnaldo Carvalho de Melo (3):
>       perf symbols: Try the .debug/ DSO cache as a last resort
>       perf ui browsers: Remove help messages about use of right and arrow keys
>       perf hists browser: Inform how to reset the symbol filter
> 
> Jiri Olsa (2):
>       tools include: Fix strict-aliasing rules breakage
>       tools build: Fix cross compile build
> 
> Namhyung Kim (1):
>       perf hists browser: Add 'm' key for context menu display
> 
> Rabin Vincent (2):
>       perf callchain: Use debug_frame if eh_frame is unusable
>       perf callchains: Fix unw_word_t pointer casts
> 
>  tools/build/Makefile.include       |  4 ++++
>  tools/include/linux/compiler.h     | 32 ++++++++++++++++++++++++--------
>  tools/perf/ui/browsers/annotate.c  |  6 +++---
>  tools/perf/ui/browsers/hists.c     | 13 ++++++++-----
>  tools/perf/ui/browsers/map.c       |  2 +-
>  tools/perf/ui/browsers/scripts.c   |  2 +-
>  tools/perf/util/symbol.c           | 18 +++++++++---------
>  tools/perf/util/unwind-libunwind.c | 14 ++++++++------
>  8 files changed, 58 insertions(+), 33 deletions(-)

Pulled, thanks a lot Arnaldo!

	Ingo

[GIT PULL 0/8] perf/core improvements and fixes

[Arnaldo Carvalho de Melo]

Hi Ingo,

	Please consider pulling,

- Arnaldo

The following changes since commit 4ba792e303e278052bb0ee60cce15d6d7dc15c7c:

  Merge tag 'perf-core-for-mingo' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/core (2015-10-22 09:33:46 +0200)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git tags/perf-core-for-mingo

for you to fetch changes up to f06cff7c59b6b252d667435d7baad48687b41002:

  perf annotate: Don't die() when finding an invalid config option (2015-10-22 18:10:52 -0300)

----------------------------------------------------------------
perf/core improvements and fixes:

User visible:

- The default for callchains is back to 'callee' when --children is not used,
  (Namhyung Kim)

- Move the 'use_offset' option to the right place where the annotate code
  expects it to be to be able to properly handle it (Namhyung Kim)

- Don't die when an unknown 'annotate' option is found in the perf config
  file (usually ~/.perfconfig), just warn the user (Arnaldo Carvalho de Melo)

Infrastructure:

- Support %ps/%pS in libtraceevent (Scott Wood)

Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>

----------------------------------------------------------------
Arnaldo Carvalho de Melo (2):
      perf ui tui: Register the error callbacks before initializing the widgets
      perf annotate: Don't die() when finding an invalid config option

Namhyung Kim (5):
      perf tools: Move callchain help messages to callchain.h
      perf top: Support call-graph display options also
      perf tools: Defaults to 'caller' callchain order only if --children is enabled
      perf tools: Improve call graph documents and help messages
      perf annotate: Fix 'annotate.use_offset' config variable usage

Scott Wood (1):
      tools lib traceevent: Support %ps/%pS

 tools/lib/traceevent/event-parse.c       |  4 +--
 tools/perf/Documentation/perf-record.txt |  9 +++++--
 tools/perf/Documentation/perf-report.txt | 38 ++++++++++++++++++-----------
 tools/perf/Documentation/perf-top.txt    |  5 ++--
 tools/perf/builtin-record.c              | 11 +++------
 tools/perf/builtin-report.c              | 17 ++++++++++---
 tools/perf/builtin-top.c                 | 30 +++++++++++++++++++----
 tools/perf/ui/browsers/annotate.c        |  8 +++---
 tools/perf/ui/tui/setup.c                |  8 +++---
 tools/perf/util/callchain.c              | 42 +++++++++++++++++++++++++++++---
 tools/perf/util/callchain.h              | 26 ++++++++++++++++++++
 tools/perf/util/util.c                   |  2 +-
 12 files changed, 151 insertions(+), 49 deletions(-)

Re: [GIT PULL 0/8] perf/core improvements and fixes

[Ingo Molnar]

* Arnaldo Carvalho de Melo <acme@kernel.org> wrote:

> Hi Ingo,
> 
> 	Please consider pulling,
> 
> - Arnaldo
> 
> The following changes since commit 4ba792e303e278052bb0ee60cce15d6d7dc15c7c:
> 
>   Merge tag 'perf-core-for-mingo' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/core (2015-10-22 09:33:46 +0200)
> 
> are available in the git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git tags/perf-core-for-mingo
> 
> for you to fetch changes up to f06cff7c59b6b252d667435d7baad48687b41002:
> 
>   perf annotate: Don't die() when finding an invalid config option (2015-10-22 18:10:52 -0300)
> 
> ----------------------------------------------------------------
> perf/core improvements and fixes:
> 
> User visible:
> 
> - The default for callchains is back to 'callee' when --children is not used,
>   (Namhyung Kim)
> 
> - Move the 'use_offset' option to the right place where the annotate code
>   expects it to be to be able to properly handle it (Namhyung Kim)
> 
> - Don't die when an unknown 'annotate' option is found in the perf config
>   file (usually ~/.perfconfig), just warn the user (Arnaldo Carvalho de Melo)
> 
> Infrastructure:
> 
> - Support %ps/%pS in libtraceevent (Scott Wood)
> 
> Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> 
> ----------------------------------------------------------------
> Arnaldo Carvalho de Melo (2):
>       perf ui tui: Register the error callbacks before initializing the widgets
>       perf annotate: Don't die() when finding an invalid config option
> 
> Namhyung Kim (5):
>       perf tools: Move callchain help messages to callchain.h
>       perf top: Support call-graph display options also
>       perf tools: Defaults to 'caller' callchain order only if --children is enabled
>       perf tools: Improve call graph documents and help messages
>       perf annotate: Fix 'annotate.use_offset' config variable usage
> 
> Scott Wood (1):
>       tools lib traceevent: Support %ps/%pS
> 
>  tools/lib/traceevent/event-parse.c       |  4 +--
>  tools/perf/Documentation/perf-record.txt |  9 +++++--
>  tools/perf/Documentation/perf-report.txt | 38 ++++++++++++++++++-----------
>  tools/perf/Documentation/perf-top.txt    |  5 ++--
>  tools/perf/builtin-record.c              | 11 +++------
>  tools/perf/builtin-report.c              | 17 ++++++++++---
>  tools/perf/builtin-top.c                 | 30 +++++++++++++++++++----
>  tools/perf/ui/browsers/annotate.c        |  8 +++---
>  tools/perf/ui/tui/setup.c                |  8 +++---
>  tools/perf/util/callchain.c              | 42 +++++++++++++++++++++++++++++---
>  tools/perf/util/callchain.h              | 26 ++++++++++++++++++++
>  tools/perf/util/util.c                   |  2 +-
>  12 files changed, 151 insertions(+), 49 deletions(-)

Pulled, thanks a lot Arnaldo!

	Ingo

[GIT PULL 0/8] perf/core improvements and fixes

[Arnaldo Carvalho de Melo]

Hi Ingo,

	This one gets us to pass .c files that gets built and
loaded, next step will be to be able to access function arguments,
for which there are patches available, but I'm still reviewing them.

	Please consider pulling,

- Arnaldo

The following changes since commit 66a565c203bc31b76969711fbd92da11bee2f129:

  Merge tag 'perf-ebpf-for-mingo' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/core (2015-10-29 13:17:56 +0100)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git tags/perf-core-for-mingo

for you to fetch changes up to 7ed4915ad60788d6b846e2cd034f49ee15698143:

  perf unwind: Pass symbol source to libunwind (2015-10-29 17:48:38 -0300)

----------------------------------------------------------------
perf/core improvements and fixes:

New features:

- Allow passing C language eBPF scriptlets via --event in all tools,
  so that it gets built using clang and then pass it to the kernel via
  sys_bpf() (Wang Nan)

- Wire up the loaded ebpf object file with associated kprobes, so that
  it can determine if the kprobes will be filtered or not (Wang Nan)

User visible:

- Add cmd string table to decode sys_bpf first arg in 'trace' (Arnaldo Carvalho de Melo)

- Enable printing of branch stack in 'perf script' (Stephane Eranian)

- Pass the right file with debug info to libunwind (Rabin Vincent)

Build Fixes:

- Make sure fixdep is built before libbpf, fixing a race (Jiri Olsa)

- Fix libiberty feature detection (Rabin Vincent)

Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>

----------------------------------------------------------------
Arnaldo Carvalho de Melo (1):
      perf trace: Add cmd string table to decode sys_bpf first arg

Jiri Olsa (1):
      perf tools: Make sure fixdep is built before libbpf

Rabin Vincent (2):
      tools build: Fix libiberty feature detection
      perf unwind: Pass symbol source to libunwind

Stephane Eranian (1):
      perf script: Enable printing of branch stack

Wang Nan (3):
      perf bpf: Attach eBPF filter to perf event
      perf record: Add clang options for compiling BPF scripts
      perf tools: Compile scriptlets to BPF objects when passing '.c' to --event

 tools/build/feature/Makefile             |  4 +-
 tools/perf/Documentation/perf-record.txt |  6 +++
 tools/perf/Documentation/perf-script.txt | 14 +++++-
 tools/perf/Makefile.perf                 |  2 +-
 tools/perf/builtin-record.c              |  7 +++
 tools/perf/builtin-script.c              | 82 +++++++++++++++++++++++++++++++-
 tools/perf/builtin-trace.c               |  7 +++
 tools/perf/tests/bpf-script-example.c    | 44 +++++++++++++++++
 tools/perf/util/bpf-loader.c             | 17 ++++++-
 tools/perf/util/bpf-loader.h             |  5 +-
 tools/perf/util/evsel.c                  | 17 +++++++
 tools/perf/util/evsel.h                  |  1 +
 tools/perf/util/parse-events.c           | 11 ++++-
 tools/perf/util/parse-events.h           |  3 +-
 tools/perf/util/parse-events.l           |  3 ++
 tools/perf/util/parse-events.y           | 15 +++++-
 tools/perf/util/unwind-libunwind.c       |  5 +-
 17 files changed, 227 insertions(+), 16 deletions(-)
 create mode 100644 tools/perf/tests/bpf-script-example.c

Re: [GIT PULL 0/8] perf/core improvements and fixes

[Ingo Molnar]

* Arnaldo Carvalho de Melo <acme@kernel.org> wrote:

> Hi Ingo,
> 
> 	This one gets us to pass .c files that gets built and
> loaded, next step will be to be able to access function arguments,
> for which there are patches available, but I'm still reviewing them.
> 
> 	Please consider pulling,
> 
> - Arnaldo
> 
> The following changes since commit 66a565c203bc31b76969711fbd92da11bee2f129:
> 
>   Merge tag 'perf-ebpf-for-mingo' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/core (2015-10-29 13:17:56 +0100)
> 
> are available in the git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git tags/perf-core-for-mingo
> 
> for you to fetch changes up to 7ed4915ad60788d6b846e2cd034f49ee15698143:
> 
>   perf unwind: Pass symbol source to libunwind (2015-10-29 17:48:38 -0300)
> 
> ----------------------------------------------------------------
> perf/core improvements and fixes:
> 
> New features:
> 
> - Allow passing C language eBPF scriptlets via --event in all tools,
>   so that it gets built using clang and then pass it to the kernel via
>   sys_bpf() (Wang Nan)
> 
> - Wire up the loaded ebpf object file with associated kprobes, so that
>   it can determine if the kprobes will be filtered or not (Wang Nan)
> 
> User visible:
> 
> - Add cmd string table to decode sys_bpf first arg in 'trace' (Arnaldo Carvalho de Melo)
> 
> - Enable printing of branch stack in 'perf script' (Stephane Eranian)
> 
> - Pass the right file with debug info to libunwind (Rabin Vincent)
> 
> Build Fixes:
> 
> - Make sure fixdep is built before libbpf, fixing a race (Jiri Olsa)
> 
> - Fix libiberty feature detection (Rabin Vincent)
> 
> Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> 
> ----------------------------------------------------------------
> Arnaldo Carvalho de Melo (1):
>       perf trace: Add cmd string table to decode sys_bpf first arg
> 
> Jiri Olsa (1):
>       perf tools: Make sure fixdep is built before libbpf
> 
> Rabin Vincent (2):
>       tools build: Fix libiberty feature detection
>       perf unwind: Pass symbol source to libunwind
> 
> Stephane Eranian (1):
>       perf script: Enable printing of branch stack
> 
> Wang Nan (3):
>       perf bpf: Attach eBPF filter to perf event
>       perf record: Add clang options for compiling BPF scripts
>       perf tools: Compile scriptlets to BPF objects when passing '.c' to --event
> 
>  tools/build/feature/Makefile             |  4 +-
>  tools/perf/Documentation/perf-record.txt |  6 +++
>  tools/perf/Documentation/perf-script.txt | 14 +++++-
>  tools/perf/Makefile.perf                 |  2 +-
>  tools/perf/builtin-record.c              |  7 +++
>  tools/perf/builtin-script.c              | 82 +++++++++++++++++++++++++++++++-
>  tools/perf/builtin-trace.c               |  7 +++
>  tools/perf/tests/bpf-script-example.c    | 44 +++++++++++++++++
>  tools/perf/util/bpf-loader.c             | 17 ++++++-
>  tools/perf/util/bpf-loader.h             |  5 +-
>  tools/perf/util/evsel.c                  | 17 +++++++
>  tools/perf/util/evsel.h                  |  1 +
>  tools/perf/util/parse-events.c           | 11 ++++-
>  tools/perf/util/parse-events.h           |  3 +-
>  tools/perf/util/parse-events.l           |  3 ++
>  tools/perf/util/parse-events.y           | 15 +++++-
>  tools/perf/util/unwind-libunwind.c       |  5 +-
>  17 files changed, 227 insertions(+), 16 deletions(-)
>  create mode 100644 tools/perf/tests/bpf-script-example.c

Pulled, thanks a lot Arnaldo!

	Ingo

[GIT PULL 0/8] perf/core improvements and fixes

[Arnaldo Carvalho de Melo]

Hi Ingo,

	Please consider pulling,

- Arnaldo

The following changes since commit c36608843adf4674c462e49f63b64b2987d0ba0b:

  Merge tag 'perf-core-for-mingo' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/urgent (2016-01-13 10:36:03 +0100)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git tags/perf-core-for-mingo

for you to fetch changes up to 96b9e70b8e6cd65f71ee71889143976f3afb038a:

  perf build: Introduce FEATURES_DUMP make variable (2016-01-15 16:32:00 -0300)

----------------------------------------------------------------
perf tools improvements and fixes:

User visible bug fixes:

- Fix reading of build-id from vDSO (Ben Hutchings)

- Fix processing samples for guests, noticed with 'perf kvm',
  but noticeable as well via other tools, such as 'perf top'
  (Ravi Bangoria)

Build infrastructure:

- Add feature-dump target and FEATURES_DUMP make variable, to
  allow reusing the feature detection results among multiple
  tools/ living codebases, such as perf and lib/bpf (Jiri Olsa)

- 'make -C tools/perf build-test' improvements, making it more
  paralelizable and allowing building it outside of the source
  tree, using O= (Wang Nan)

Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>

----------------------------------------------------------------
Ben Hutchings (1):
      perf symbols: Fix reading of build-id from vDSO

Jiri Olsa (2):
      perf build: Add feature-dump target
      perf build: Introduce FEATURES_DUMP make variable

Ravi Bangoria (1):
      perf kvm record/report: 'unprocessable sample' error while recording/reporting guest data

Wang Nan (4):
      perf build: Set parallel making options build-test
      perf build: Pass O option to Makefile.perf in build-test
      perf build: Test correct path of perf in build-test
      perf build: Pass O option to kernel makefile in build-test

 tools/perf/Makefile.perf   | 25 ++++++++++++++++++++-
 tools/perf/config/Makefile |  4 ++++
 tools/perf/tests/make      | 55 +++++++++++++++++++++++++++++++++-------------
 tools/perf/util/session.c  |  2 +-
 tools/perf/util/symbol.c   |  2 +-
 5 files changed, 70 insertions(+), 18 deletions(-)

Re: [GIT PULL 0/8] perf/core improvements and fixes

[Ingo Molnar]

* Arnaldo Carvalho de Melo <acme@kernel.org> wrote:

> Hi Ingo,
> 
> 	Please consider pulling,
> 
> - Arnaldo
> 
> The following changes since commit c36608843adf4674c462e49f63b64b2987d0ba0b:
> 
>   Merge tag 'perf-core-for-mingo' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/urgent (2016-01-13 10:36:03 +0100)
> 
> are available in the git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git tags/perf-core-for-mingo
> 
> for you to fetch changes up to 96b9e70b8e6cd65f71ee71889143976f3afb038a:
> 
>   perf build: Introduce FEATURES_DUMP make variable (2016-01-15 16:32:00 -0300)
> 
> ----------------------------------------------------------------
> perf tools improvements and fixes:
> 
> User visible bug fixes:
> 
> - Fix reading of build-id from vDSO (Ben Hutchings)
> 
> - Fix processing samples for guests, noticed with 'perf kvm',
>   but noticeable as well via other tools, such as 'perf top'
>   (Ravi Bangoria)
> 
> Build infrastructure:
> 
> - Add feature-dump target and FEATURES_DUMP make variable, to
>   allow reusing the feature detection results among multiple
>   tools/ living codebases, such as perf and lib/bpf (Jiri Olsa)
> 
> - 'make -C tools/perf build-test' improvements, making it more
>   paralelizable and allowing building it outside of the source
>   tree, using O= (Wang Nan)
> 
> Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> 
> ----------------------------------------------------------------
> Ben Hutchings (1):
>       perf symbols: Fix reading of build-id from vDSO
> 
> Jiri Olsa (2):
>       perf build: Add feature-dump target
>       perf build: Introduce FEATURES_DUMP make variable
> 
> Ravi Bangoria (1):
>       perf kvm record/report: 'unprocessable sample' error while recording/reporting guest data
> 
> Wang Nan (4):
>       perf build: Set parallel making options build-test
>       perf build: Pass O option to Makefile.perf in build-test
>       perf build: Test correct path of perf in build-test
>       perf build: Pass O option to kernel makefile in build-test
> 
>  tools/perf/Makefile.perf   | 25 ++++++++++++++++++++-
>  tools/perf/config/Makefile |  4 ++++
>  tools/perf/tests/make      | 55 +++++++++++++++++++++++++++++++++-------------
>  tools/perf/util/session.c  |  2 +-
>  tools/perf/util/symbol.c   |  2 +-
>  5 files changed, 70 insertions(+), 18 deletions(-)

Pulled, thanks a lot Arnaldo!

	Ingo

[GIT PULL 0/8] perf/core improvements and fixes

[Arnaldo Carvalho de Melo]

Hi Ingo,

	I pulled tip/perf/urgent to pick up fixes, please consider
pulling, I've been away for a while, so I'll be harvesting outstanding
patches in the next few days, as well as trying and reviewing more
complex patchkits,

- Arnaldo

Test results at the end of this message, as usual.

The following changes since commit c976a7d6db215481261b63a89a408cb265a9812b:

  Merge remote-tracking branch 'tip/perf/urgent' into perf/core, to pick up fixes (2017-10-02 13:58:12 -0300)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git tags/perf-core-for-mingo-4.15-20171003

for you to fetch changes up to f6a9820d572bd8384d982357cbad214b3a6c04bb:

  perf tests attr: Fix group stat tests (2017-10-03 09:41:45 -0300)

----------------------------------------------------------------
perf/core improvements and fixes:

- Multithread the synthesizing of PERF_RECORD_ events for pre-existing
  threads in 'perf top', speeding up that phase, greatly improving the
  user experience in systems such as Intel's Knights Mill (Kan Liang)

- 'perf test' fixes for the perf_event_attr test case (Jiri Olsa, Thomas Richter)

Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>

----------------------------------------------------------------
Jiri Olsa (2):
      perf tests attr: Fix task term values
      perf tests attr: Fix group stat tests

Kan Liang (4):
      perf tools: Lock to protect namespaces and comm list
      perf tools: Lock to protect comm_str rb tree
      perf top: Implement multithreading for perf_event__synthesize_threads
      perf top: Add option to set the number of thread for event synthesize

Thomas Richter (2):
      perf test attr: Fix python error on empty result
      perf test attr: Fix ignored test case result

 tools/perf/Documentation/perf-top.txt            |   3 +
 tools/perf/builtin-kvm.c                         |   3 +-
 tools/perf/builtin-record.c                      |   2 +-
 tools/perf/builtin-top.c                         |  13 +-
 tools/perf/builtin-trace.c                       |   2 +-
 tools/perf/tests/attr.c                          |   2 +-
 tools/perf/tests/attr.py                         |   6 +-
 tools/perf/tests/attr/base-record                |   2 +-
 tools/perf/tests/attr/test-record-group          |   1 +
 tools/perf/tests/attr/test-record-group-sampling |   2 +-
 tools/perf/tests/attr/test-record-group1         |   1 +
 tools/perf/tests/attr/test-stat-group            |   2 +
 tools/perf/tests/attr/test-stat-group1           |   2 +
 tools/perf/tests/mmap-thread-lookup.c            |   2 +-
 tools/perf/util/comm.c                           |  18 ++-
 tools/perf/util/event.c                          | 163 ++++++++++++++++++-----
 tools/perf/util/event.h                          |   3 +-
 tools/perf/util/machine.c                        |   8 +-
 tools/perf/util/machine.h                        |   9 +-
 tools/perf/util/thread.c                         |  53 +++++++-
 tools/perf/util/thread.h                         |   3 +
 tools/perf/util/top.h                            |   1 +
 22 files changed, 249 insertions(+), 52 deletions(-)

Test results:

The first ones are container (docker) based builds of tools/perf with and
without libelf support.  Where clang is available, it is also used to build
perf with/without libelf.

The objtool and samples/bpf/ builds are disabled now that I'm switching from
using the sources in a local volume to fetching them from a http server to
build it inside the container, to make it easier to build in a container cluster.
Those will come back later.

Several are cross builds, the ones with -x-ARCH and the android one, and those
may not have all the features built, due to lack of multi-arch devel packages,
available and being used so far on just a few, like
debian:experimental-x-{arm64,mipsel}.

The 'perf test' one will perform a variety of tests exercising
tools/perf/util/, tools/lib/{bpf,traceevent,etc}, as well as run perf commands
with a variety of command line event specifications to then intercept the
sys_perf_event syscall to check that the perf_event_attr fields are set up as
expected, among a variety of other unit tests.

Then there is the 'make -C tools/perf build-test' ones, that build tools/perf/
with a variety of feature sets, exercising the build with an incomplete set of
features as well as with a complete one. It is planned to have it run on each
of the containers mentioned above, using some container orchestration
infrastructure. Get in contact if interested in helping having this in place.

  # dm
   1 alpine:3.4: Ok
   2 alpine:3.5: Ok
   3 alpine:3.6: Ok
   4 alpine:edge: Ok
   5 android-ndk:r12b-arm: Ok
   6 android-ndk:r15c-arm: Ok
   7 centos:5: Ok
   8 centos:6: Ok
   9 centos:7: Ok
  10 debian:7: Ok
  11 debian:8: Ok
  12 debian:9: Ok
  13 debian:experimental: Ok
  14 debian:experimental-x-arm64: Ok
  15 debian:experimental-x-mips: Ok
  16 debian:experimental-x-mips64: Ok
  17 debian:experimental-x-mipsel: Ok
  18 fedora:20: Ok
  19 fedora:21: Ok
  20 fedora:22: Ok
  21 fedora:23: Ok
  22 fedora:24: Ok
  23 fedora:24-x-ARC-uClibc: FAIL

builtin-sched.c: In function 'timehist_sched_switch_event':
builtin-sched.c:2580:1: internal compiler error: in change_address_1, at emit-rtl.c:2150
 }
 ^
Please submit a full bug report,
with preprocessed source if appropriate.
See <https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/issues> for instructions.

  24 fedora:25: Ok
  25 fedora:26: Ok
  26 fedora:rawhide: Ok
  27 mageia:5: Ok
  28 opensuse:42.1: Ok
  29 opensuse:42.2: Ok
  30 opensuse:42.3: Ok
  31 opensuse:tumbleweed: Ok
  32 oraclelinux:6: Ok
  33 oraclelinux:7: Ok
  34 ubuntu:12.04.5: Ok
  35 ubuntu:14.04.4: Ok
  36 ubuntu:14.04.4-x-linaro-arm64: Ok
  37 ubuntu:15.10: Ok
  38 ubuntu:16.04: Ok
  39 ubuntu:16.04-x-arm: Ok
  40 ubuntu:16.04-x-arm64: Ok
  41 ubuntu:16.04-x-powerpc: Ok
  42 ubuntu:16.04-x-powerpc64: Ok
  43 ubuntu:16.04-x-powerpc64el: Ok
  44 ubuntu:16.04-x-s390: Ok

  # uname -a
  Linux jouet 4.13.0+ #3 SMP Mon Sep 25 11:51:22 -03 2017 x86_64 x86_64 x86_64 GNU/Linux
  # perf test
   1: vmlinux symtab matches kallsyms                       : Ok
   2: Detect openat syscall event                           : Ok
   3: Detect openat syscall event on all cpus               : Ok
   4: Read samples using the mmap interface                 : Ok
   5: Test data source output                               : Ok
   6: Parse event definition strings                        : Ok
   7: Simple expression parser                              : Ok
   8: PERF_RECORD_* events & perf_sample fields             : Ok
   9: Parse perf pmu format                                 : Ok
  10: DSO data read                                         : Ok
  11: DSO data cache                                        : Ok
  12: DSO data reopen                                       : Ok
  13: Roundtrip evsel->name                                 : Ok
  14: Parse sched tracepoints fields                        : Ok
  15: syscalls:sys_enter_openat event fields                : Ok
  16: Setup struct perf_event_attr                          : Ok
  17: Match and link multiple hists                         : Ok
  18: 'import perf' in python                               : Ok
  19: Breakpoint overflow signal handler                    : Ok
  20: Breakpoint overflow sampling                          : Ok
  21: Number of exit events of a simple workload            : Ok
  22: Software clock events period values                   : Ok
  23: Object code reading                                   : Ok
  24: Sample parsing                                        : Ok
  25: Use a dummy software event to keep tracking           : Ok
  26: Parse with no sample_id_all bit set                   : Ok
  27: Filter hist entries                                   : Ok
  28: Lookup mmap thread                                    : Ok
  29: Share thread mg                                       : Ok
  30: Sort output of hist entries                           : Ok
  31: Cumulate child hist entries                           : Ok
  32: Track with sched_switch                               : Ok
  33: Filter fds with revents mask in a fdarray             : Ok
  34: Add fd to a fdarray, making it autogrow               : Ok
  35: kmod_path__parse                                      : Ok
  36: Thread map                                            : Ok
  37: LLVM search and compile                               :
  37.1: Basic BPF llvm compile                              : Ok
  37.2: kbuild searching                                    : Ok
  37.3: Compile source for BPF prologue generation          : Ok
  37.4: Compile source for BPF relocation                   : Ok
  38: Session topology                                      : Ok
  39: BPF filter                                            :
  39.1: Basic BPF filtering                                 : Ok
  39.2: BPF pinning                                         : Ok
  39.3: BPF prologue generation                             : Ok
  39.4: BPF relocation checker                              : Ok
  40: Synthesize thread map                                 : Ok
  41: Remove thread map                                     : Ok
  42: Synthesize cpu map                                    : Ok
  43: Synthesize stat config                                : Ok
  44: Synthesize stat                                       : Ok
  45: Synthesize stat round                                 : Ok
  46: Synthesize attr update                                : Ok
  47: Event times                                           : Ok
  48: Read backward ring buffer                             : Ok
  49: Print cpu map                                         : Ok
  50: Probe SDT events                                      : Ok
  51: is_printable_array                                    : Ok
  52: Print bitmap                                          : Ok
  53: perf hooks                                            : Ok
  54: builtin clang support                                 : Skip (not compiled in)
  55: unit_number__scnprintf                                : Ok
  56: x86 rdpmc                                             : Ok
  57: Convert perf time to TSC                              : Ok
  58: DWARF unwind                                          : Ok
  59: x86 instruction decoder - new instructions            : Ok
  60: Use vfs_getname probe to get syscall args filenames   : Ok
  61: probe libc's inet_pton & backtrace it with ping       : Ok
  62: Check open filename arg using perf trace + vfs_getname: Ok
  63: Add vfs_getname probe to get syscall args filenames   : Ok
  #

Re: [GIT PULL 0/8] perf/core improvements and fixes

[Ingo Molnar]

* Arnaldo Carvalho de Melo <acme@kernel.org> wrote:

> Hi Ingo,
> 
> 	I pulled tip/perf/urgent to pick up fixes, please consider
> pulling, I've been away for a while, so I'll be harvesting outstanding
> patches in the next few days, as well as trying and reviewing more
> complex patchkits,
> 
> - Arnaldo
> 
> Test results at the end of this message, as usual.
> 
> The following changes since commit c976a7d6db215481261b63a89a408cb265a9812b:
> 
>   Merge remote-tracking branch 'tip/perf/urgent' into perf/core, to pick up fixes (2017-10-02 13:58:12 -0300)
> 
> are available in the git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git tags/perf-core-for-mingo-4.15-20171003
> 
> for you to fetch changes up to f6a9820d572bd8384d982357cbad214b3a6c04bb:
> 
>   perf tests attr: Fix group stat tests (2017-10-03 09:41:45 -0300)
> 
> ----------------------------------------------------------------
> perf/core improvements and fixes:
> 
> - Multithread the synthesizing of PERF_RECORD_ events for pre-existing
>   threads in 'perf top', speeding up that phase, greatly improving the
>   user experience in systems such as Intel's Knights Mill (Kan Liang)
> 
> - 'perf test' fixes for the perf_event_attr test case (Jiri Olsa, Thomas Richter)
> 
> Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> 
> ----------------------------------------------------------------
> Jiri Olsa (2):
>       perf tests attr: Fix task term values
>       perf tests attr: Fix group stat tests
> 
> Kan Liang (4):
>       perf tools: Lock to protect namespaces and comm list
>       perf tools: Lock to protect comm_str rb tree
>       perf top: Implement multithreading for perf_event__synthesize_threads
>       perf top: Add option to set the number of thread for event synthesize
> 
> Thomas Richter (2):
>       perf test attr: Fix python error on empty result
>       perf test attr: Fix ignored test case result
> 
>  tools/perf/Documentation/perf-top.txt            |   3 +
>  tools/perf/builtin-kvm.c                         |   3 +-
>  tools/perf/builtin-record.c                      |   2 +-
>  tools/perf/builtin-top.c                         |  13 +-
>  tools/perf/builtin-trace.c                       |   2 +-
>  tools/perf/tests/attr.c                          |   2 +-
>  tools/perf/tests/attr.py                         |   6 +-
>  tools/perf/tests/attr/base-record                |   2 +-
>  tools/perf/tests/attr/test-record-group          |   1 +
>  tools/perf/tests/attr/test-record-group-sampling |   2 +-
>  tools/perf/tests/attr/test-record-group1         |   1 +
>  tools/perf/tests/attr/test-stat-group            |   2 +
>  tools/perf/tests/attr/test-stat-group1           |   2 +
>  tools/perf/tests/mmap-thread-lookup.c            |   2 +-
>  tools/perf/util/comm.c                           |  18 ++-
>  tools/perf/util/event.c                          | 163 ++++++++++++++++++-----
>  tools/perf/util/event.h                          |   3 +-
>  tools/perf/util/machine.c                        |   8 +-
>  tools/perf/util/machine.h                        |   9 +-
>  tools/perf/util/thread.c                         |  53 +++++++-
>  tools/perf/util/thread.h                         |   3 +
>  tools/perf/util/top.h                            |   1 +
>  22 files changed, 249 insertions(+), 52 deletions(-)

Pulled, thanks a lot Arnaldo!

	Ingo

[GIT PULL 0/8] perf/core improvements and fixes

[Arnaldo Carvalho de Melo]

Hi Ingo,

	Please consider pulling,

- Arnaldo

Test results at the end of this message, as usual.

The following changes since commit 631fe154edb0a37308d0116a0f9b7bba9dca6218:

  perf/x86: Update rdpmc_always_available static key to the modern API (2018-03-27 07:53:00 +0200)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git tags/perf-core-for-mingo-4.17-20180328

for you to fetch changes up to 109d59b900e78834c66657dd4748fcedb9a1fe8d:

  perf vendor events s390: Add JSON files for IBM z14 (2018-03-27 13:13:39 -0300)

----------------------------------------------------------------
perf/core improvements and fixes:

- Be consistent when checking if a perf_mmap instance had
  its ring buffer unmmaped, fixing segfaults noticed in
  'perf trace' (Kan Liang, Arnaldo Carvalho de Melo)

- Avoid adding the same option multiple times to the 'diff'
  command in check-headers.sh (Jiri Olsa)

- Add vendor event files (JSON format) to various IBM
  s390 models (z10EC, z10BC, z196, zEC12, zBC12, z13
  and z14) (Thomas Richter)

Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>

----------------------------------------------------------------
Arnaldo Carvalho de Melo (1):
      perf mmap: Be consistent when checking for an unmaped ring buffer

Jiri Olsa (1):
      perf build: Fix check-headers.sh opts assignment

Kan Liang (1):
      perf mmap: Fix accessing unmapped mmap in perf_mmap__read_done()

Thomas Richter (5):
      perf vendor events s390: Add JSON files for IBM z10EC z10BC
      perf vendor events s390: Add JSON files for IBM z196
      perf vendor events s390: Add JSON files for IBM zEC12 zBC12
      perf vendor events s390: Add JSON files for IBM z13
      perf vendor events s390: Add JSON files for IBM z14

 tools/perf/check-headers.sh                        |   1 +
 tools/perf/pmu-events/arch/s390/cf_z10/basic.json  |  74 +++++
 tools/perf/pmu-events/arch/s390/cf_z10/crypto.json |  98 ++++++
 .../perf/pmu-events/arch/s390/cf_z10/extended.json | 110 +++++++
 tools/perf/pmu-events/arch/s390/cf_z13/basic.json  |  74 +++++
 tools/perf/pmu-events/arch/s390/cf_z13/crypto.json |  98 ++++++
 .../perf/pmu-events/arch/s390/cf_z13/extended.json | 338 +++++++++++++++++++++
 tools/perf/pmu-events/arch/s390/cf_z14/basic.json  |  50 +++
 tools/perf/pmu-events/arch/s390/cf_z14/crypto.json |  98 ++++++
 .../perf/pmu-events/arch/s390/cf_z14/extended.json | 320 +++++++++++++++++++
 tools/perf/pmu-events/arch/s390/cf_z196/basic.json |  74 +++++
 .../perf/pmu-events/arch/s390/cf_z196/crypto.json  |  98 ++++++
 .../pmu-events/arch/s390/cf_z196/extended.json     | 146 +++++++++
 .../perf/pmu-events/arch/s390/cf_zec12/basic.json  |  74 +++++
 .../perf/pmu-events/arch/s390/cf_zec12/crypto.json |  98 ++++++
 .../pmu-events/arch/s390/cf_zec12/extended.json    | 212 +++++++++++++
 tools/perf/pmu-events/arch/s390/mapfile.csv        |   6 +
 tools/perf/util/mmap.c                             |  19 +-
 18 files changed, 1987 insertions(+), 1 deletion(-)
 create mode 100644 tools/perf/pmu-events/arch/s390/cf_z10/basic.json
 create mode 100644 tools/perf/pmu-events/arch/s390/cf_z10/crypto.json
 create mode 100644 tools/perf/pmu-events/arch/s390/cf_z10/extended.json
 create mode 100644 tools/perf/pmu-events/arch/s390/cf_z13/basic.json
 create mode 100644 tools/perf/pmu-events/arch/s390/cf_z13/crypto.json
 create mode 100644 tools/perf/pmu-events/arch/s390/cf_z13/extended.json
 create mode 100644 tools/perf/pmu-events/arch/s390/cf_z14/basic.json
 create mode 100644 tools/perf/pmu-events/arch/s390/cf_z14/crypto.json
 create mode 100644 tools/perf/pmu-events/arch/s390/cf_z14/extended.json
 create mode 100644 tools/perf/pmu-events/arch/s390/cf_z196/basic.json
 create mode 100644 tools/perf/pmu-events/arch/s390/cf_z196/crypto.json
 create mode 100644 tools/perf/pmu-events/arch/s390/cf_z196/extended.json
 create mode 100644 tools/perf/pmu-events/arch/s390/cf_zec12/basic.json
 create mode 100644 tools/perf/pmu-events/arch/s390/cf_zec12/crypto.json
 create mode 100644 tools/perf/pmu-events/arch/s390/cf_zec12/extended.json
 create mode 100644 tools/perf/pmu-events/arch/s390/mapfile.csv

Test results:

The first ones are container (docker) based builds of tools/perf with and
without libelf support.  Where clang is available, it is also used to build
perf with/without libelf.

The objtool and samples/bpf/ builds are disabled now that I'm switching from
using the sources in a local volume to fetching them from a http server to
build it inside the container, to make it easier to build in a container cluster.
Those will come back later.

Several are cross builds, the ones with -x-ARCH and the android one, and those
may not have all the features built, due to lack of multi-arch devel packages,
available and being used so far on just a few, like
debian:experimental-x-{arm64,mipsel}.

The 'perf test' one will perform a variety of tests exercising
tools/perf/util/, tools/lib/{bpf,traceevent,etc}, as well as run perf commands
with a variety of command line event specifications to then intercept the
sys_perf_event syscall to check that the perf_event_attr fields are set up as
expected, among a variety of other unit tests.

Then there is the 'make -C tools/perf build-test' ones, that build tools/perf/
with a variety of feature sets, exercising the build with an incomplete set of
features as well as with a complete one. It is planned to have it run on each
of the containers mentioned above, using some container orchestration
infrastructure. Get in contact if interested in helping having this in place.

  # docker images | grep none
  # time dm
   1 alpine:3.4                    : Ok   gcc (Alpine 5.3.0) 5.3.0
   2 alpine:3.5                    : Ok   gcc (Alpine 6.2.1) 6.2.1 20160822
   3 alpine:3.6                    : Ok   gcc (Alpine 6.3.0) 6.3.0
   4 alpine:3.7                    : Ok   gcc (Alpine 6.4.0) 6.4.0
   5 alpine:edge                   : Ok   gcc (Alpine 6.4.0) 6.4.0
   6 amazonlinux:1                 : Ok   gcc (GCC) 4.8.5 20150623 (Red Hat 4.8.5-11)
   7 amazonlinux:2                 : Ok   gcc (GCC) 7.2.1 20170915 (Red Hat 7.2.1-2)
   8 android-ndk:r12b-arm          : Ok   arm-linux-androideabi-gcc (GCC) 4.9.x 20150123 (prerelease)
   9 android-ndk:r15c-arm          : Ok   arm-linux-androideabi-gcc (GCC) 4.9.x 20150123 (prerelease)
  10 centos:5                      : Ok   gcc (GCC) 4.1.2 20080704 (Red Hat 4.1.2-55)
  11 centos:6                      : Ok   gcc (GCC) 4.4.7 20120313 (Red Hat 4.4.7-18)
  12 centos:7                      : Ok   gcc (GCC) 4.8.5 20150623 (Red Hat 4.8.5-16)
  13 debian:7                      : Ok   gcc (Debian 4.7.2-5) 4.7.2
  14 debian:8                      : Ok   gcc (Debian 4.9.2-10+deb8u1) 4.9.2
  15 debian:9                      : Ok   gcc (Debian 6.3.0-18+deb9u1) 6.3.0 20170516
  16 debian:experimental           : Ok   gcc (Debian 7.3.0-12) 7.3.0
  17 debian:experimental-x-arm64   : Ok   aarch64-linux-gnu-gcc (Debian 7.3.0-12) 7.3.0
  18 debian:experimental-x-mips    : Ok   mips-linux-gnu-gcc (Debian 7.3.0-12) 7.3.0
  19 debian:experimental-x-mips64  : Ok   mips64-linux-gnuabi64-gcc (Debian 7.3.0-11) 7.3.0
  20 debian:experimental-x-mipsel  : Ok   mipsel-linux-gnu-gcc (Debian 7.3.0-12) 7.3.0
  21 fedora:20                     : Ok   gcc (GCC) 4.8.3 20140911 (Red Hat 4.8.3-7)
  22 fedora:21                     : Ok   gcc (GCC) 4.9.2 20150212 (Red Hat 4.9.2-6)
  23 fedora:22                     : Ok   gcc (GCC) 5.3.1 20160406 (Red Hat 5.3.1-6)
  24 fedora:23                     : Ok   gcc (GCC) 5.3.1 20160406 (Red Hat 5.3.1-6)
  25 fedora:24                     : Ok   gcc (GCC) 6.3.1 20161221 (Red Hat 6.3.1-1)
  26 fedora:24-x-ARC-uClibc        : Ok   arc-linux-gcc (ARCompact ISA Linux uClibc toolchain 2017.09-rc2) 7.1.1 20170710
  27 fedora:25                     : Ok   gcc (GCC) 6.4.1 20170727 (Red Hat 6.4.1-1)
  28 fedora:26                     : Ok   gcc (GCC) 7.3.1 20180130 (Red Hat 7.3.1-2)
  29 fedora:27                     : Ok   gcc (GCC) 7.3.1 20180303 (Red Hat 7.3.1-5)
  30 fedora:rawhide                : Ok   gcc (GCC) 8.0.1 20180222 (Red Hat 8.0.1-0.16)
  31 gentoo-stage3-amd64:latest    : Ok   gcc (Gentoo 6.4.0-r1 p1.3) 6.4.0
  32 mageia:5                      : Ok   gcc (GCC) 4.9.2
  33 mageia:6                      : Ok   gcc (Mageia 5.5.0-1.mga6) 5.5.0
  34 opensuse:42.1                 : Ok   gcc (SUSE Linux) 4.8.5
  35 opensuse:42.2                 : Ok   gcc (SUSE Linux) 4.8.5
  36 opensuse:42.3                 : Ok   gcc (SUSE Linux) 4.8.5
  37 opensuse:tumbleweed           : Ok   gcc (SUSE Linux) 7.3.0
  38 oraclelinux:6                 : Ok   gcc (GCC) 4.4.7 20120313 (Red Hat 4.4.7-18)
  39 oraclelinux:7                 : Ok   gcc (GCC) 4.8.5 20150623 (Red Hat 4.8.5-16.0.3)
  40 ubuntu:12.04.5                : Ok   gcc (Ubuntu/Linaro 4.6.3-1ubuntu5) 4.6.3
  41 ubuntu:14.04.4                : Ok   gcc (Ubuntu 4.8.4-2ubuntu1~14.04.3) 4.8.4
  42 ubuntu:14.04.4-x-linaro-arm64 : Ok   aarch64-linux-gnu-gcc (Linaro GCC 5.4-2017.05) 5.4.1 20170404
  43 ubuntu:15.04                  : Ok   gcc (Ubuntu 4.9.2-10ubuntu13) 4.9.2
  44 ubuntu:16.04                  : Ok   gcc (Ubuntu 5.4.0-6ubuntu1~16.04.9) 5.4.0 20160609
  45 ubuntu:16.04-x-arm            : Ok   arm-linux-gnueabihf-gcc (Ubuntu/Linaro 5.4.0-6ubuntu1~16.04.9) 5.4.0 20160609
  46 ubuntu:16.04-x-arm64          : Ok   aarch64-linux-gnu-gcc (Ubuntu/Linaro 5.4.0-6ubuntu1~16.04.9) 5.4.0 20160609
  47 ubuntu:16.04-x-powerpc        : Ok   powerpc-linux-gnu-gcc (Ubuntu 5.4.0-6ubuntu1~16.04.9) 5.4.0 20160609
  48 ubuntu:16.04-x-powerpc64      : Ok   powerpc64-linux-gnu-gcc (Ubuntu/IBM 5.4.0-6ubuntu1~16.04.9) 5.4.0 20160609
  49 ubuntu:16.04-x-powerpc64el    : Ok   powerpc64le-linux-gnu-gcc (Ubuntu/IBM 5.4.0-6ubuntu1~16.04.9) 5.4.0 20160609
  50 ubuntu:16.04-x-s390           : Ok   s390x-linux-gnu-gcc (Ubuntu 5.4.0-6ubuntu1~16.04.9) 5.4.0 20160609
  51 ubuntu:16.10                  : Ok   gcc (Ubuntu 6.2.0-5ubuntu12) 6.2.0 20161005
  52 ubuntu:17.04                  : Ok   gcc (Ubuntu 6.3.0-12ubuntu2) 6.3.0 20170406
  53 ubuntu:17.10                  : Ok   gcc (Ubuntu 7.2.0-8ubuntu3) 7.2.0
  54 ubuntu:18.04                  : Ok   gcc (Ubuntu 7.2.0-16ubuntu1) 7.2.0
  #
  
  # uname -r
  4.16.0-rc7
  # perf test
   1: vmlinux symtab matches kallsyms                       : Ok
   2: Detect openat syscall event                           : Ok
   3: Detect openat syscall event on all cpus               : Ok
   4: Read samples using the mmap interface                 : Ok
   5: Test data source output                               : Ok
   6: Parse event definition strings                        : Ok
   7: Simple expression parser                              : Ok
   8: PERF_RECORD_* events & perf_sample fields             : Ok
   9: Parse perf pmu format                                 : Ok
  10: DSO data read                                         : Ok
  11: DSO data cache                                        : Ok
  12: DSO data reopen                                       : Ok
  13: Roundtrip evsel->name                                 : Ok
  14: Parse sched tracepoints fields                        : Ok
  15: syscalls:sys_enter_openat event fields                : Ok
  16: Setup struct perf_event_attr                          : Ok
  17: Match and link multiple hists                         : Ok
  18: 'import perf' in python                               : Ok
  19: Breakpoint overflow signal handler                    : Ok
  20: Breakpoint overflow sampling                          : Ok
  21: Breakpoint accounting                                 : Skip
  22: Number of exit events of a simple workload            : Ok
  23: Software clock events period values                   : Ok
  24: Object code reading                                   : Ok
  25: Sample parsing                                        : Ok
  26: Use a dummy software event to keep tracking           : Ok
  27: Parse with no sample_id_all bit set                   : Ok
  28: Filter hist entries                                   : Ok
  29: Lookup mmap thread                                    : Ok
  30: Share thread mg                                       : Ok
  31: Sort output of hist entries                           : Ok
  32: Cumulate child hist entries                           : Ok
  33: Track with sched_switch                               : Ok
  34: Filter fds with revents mask in a fdarray             : Ok
  35: Add fd to a fdarray, making it autogrow               : Ok
  36: kmod_path__parse                                      : Ok
  37: Thread map                                            : Ok
  38: LLVM search and compile                               :
  38.1: Basic BPF llvm compile                              : Ok
  38.2: kbuild searching                                    : Ok
  38.3: Compile source for BPF prologue generation          : Ok
  38.4: Compile source for BPF relocation                   : Ok
  39: Session topology                                      : Ok
  40: BPF filter                                            :
  40.1: Basic BPF filtering                                 : Ok
  40.2: BPF pinning                                         : Ok
  40.3: BPF prologue generation                             : Ok
  40.4: BPF relocation checker                              : Ok
  41: Synthesize thread map                                 : Ok
  42: Remove thread map                                     : Ok
  43: Synthesize cpu map                                    : Ok
  44: Synthesize stat config                                : Ok
  45: Synthesize stat                                       : Ok
  46: Synthesize stat round                                 : Ok
  47: Synthesize attr update                                : Ok
  48: Event times                                           : Ok
  49: Read backward ring buffer                             : Ok
  50: Print cpu map                                         : Ok
  51: Probe SDT events                                      : Ok
  52: is_printable_array                                    : Ok
  53: Print bitmap                                          : Ok
  54: perf hooks                                            : Ok
  55: builtin clang support                                 : Skip (not compiled in)
  56: unit_number__scnprintf                                : Ok
  57: mem2node                                              : Ok
  58: x86 rdpmc                                             : Ok
  59: Convert perf time to TSC                              : Ok
  60: DWARF unwind                                          : Ok
  61: x86 instruction decoder - new instructions            : Ok
  62: Use vfs_getname probe to get syscall args filenames   : Ok
  63: probe libc's inet_pton & backtrace it with ping       : Ok
  64: Check open filename arg using perf trace + vfs_getname: Ok
  65: probe libc's inet_pton & backtrace it with ping       : Ok
  66: Add vfs_getname probe to get syscall args filenames   : Ok
  #
  
  $ make -C tools/perf build-test
  make: Entering directory '/home/acme/git/perf/tools/perf'
  - tarpkg: ./tests/perf-targz-src-pkg .
                  make_no_ui_O: make NO_NEWT=1 NO_SLANG=1 NO_GTK2=1
             make_no_libperl_O: make NO_LIBPERL=1
           make_no_libbionic_O: make NO_LIBBIONIC=1
         make_install_prefix_O: make install prefix=/tmp/krava
                 make_perf_o_O: make perf.o
           make_no_libpython_O: make NO_LIBPYTHON=1
                   make_tags_O: make tags
                make_install_O: make install
                    make_doc_O: make doc
       make_util_pmu_bison_o_O: make util/pmu-bison.o
              make_no_libelf_O: make NO_LIBELF=1
            make_install_bin_O: make install-bin
           make_no_backtrace_O: make NO_BACKTRACE=1
                make_no_gtk2_O: make NO_GTK2=1
               make_no_slang_O: make NO_SLANG=1
  make_no_libdw_dwarf_unwind_O: make NO_LIBDW_DWARF_UNWIND=1
        make_with_babeltrace_O: make LIBBABELTRACE=1
                   make_help_O: make help
            make_no_demangle_O: make NO_DEMANGLE=1
              make_no_libbpf_O: make NO_LIBBPF=1
                make_minimal_O: make NO_LIBPERL=1 NO_LIBPYTHON=1 NO_NEWT=1 NO_GTK2=1 NO_DEMANGLE=1 NO_LIBELF=1 NO_LIBUNWIND=1 NO_BACKTRACE=1 NO_LIBNUMA=1 NO_LIBAUDIT=1 NO_LIBBIONIC=1 NO_LIBDW_DWARF_UNWIND=1 NO_AUXTRACE=1 NO_LIBBPF=1 NO_LIBCRYPTO=1 NO_SDT=1 NO_JVMTI=1
              make_clean_all_O: make clean all
                make_no_newt_O: make NO_NEWT=1
            make_no_libaudit_O: make NO_LIBAUDIT=1
           make_no_libunwind_O: make NO_LIBUNWIND=1
            make_no_auxtrace_O: make NO_AUXTRACE=1
                  make_debug_O: make DEBUG=1
                   make_pure_O: make
             make_no_libnuma_O: make NO_LIBNUMA=1
             make_no_scripts_O: make NO_LIBPYTHON=1 NO_LIBPERL=1
                 make_static_O: make LDFLAGS=-static
         make_with_clangllvm_O: make LIBCLANGLLVM=1
   make_install_prefix_slash_O: make install prefix=/tmp/krava/
             make_util_map_o_O: make util/map.o
  OK
  make: Leaving directory '/home/acme/git/perf/tools/perf'
  $ 

[PATCH 1/8] perf build: Fix check-headers.sh opts assignment

[Arnaldo Carvalho de Melo]

From: Jiri Olsa <jolsa@kernel.org>

Currently the "opts" variable is not zero-ed and we keep on adding to
it, ending up with:

  $ check-headers.sh 2>&1
  + opts=' "-B"'
  + opts=' "-B" "-B"'
  + opts=' "-B" "-B" "-B"'
  + opts=' "-B" "-B" "-B" "-B"'
  + opts=' "-B" "-B" "-B" "-B" "-B"'
  + opts=' "-B" "-B" "-B" "-B" "-B" "-B"'

Fix this by initializing it in the check() function, right before
starting the loop.

Signed-off-by: Jiri Olsa <jolsa@kernel.org>
Tested-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: David Ahern <dsahern@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/20180321140515.2252-1-jolsa@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/check-headers.sh | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tools/perf/check-headers.sh b/tools/perf/check-headers.sh
index bf206ffe5c45..9aff89bc7535 100755
--- a/tools/perf/check-headers.sh
+++ b/tools/perf/check-headers.sh
@@ -59,6 +59,7 @@ check () {
   file=$1
 
   shift
+  opts=
   while [ -n "$*" ]; do
     opts="$opts \"$1\""
     shift
-- 
2.14.3

[PATCH 2/8] perf mmap: Fix accessing unmapped mmap in perf_mmap__read_done()

[Arnaldo Carvalho de Melo]

From: Kan Liang <kan.liang@linux.intel.com>

There is a segmentation fault when running 'perf trace'. For example:

  [root@jouet e]# perf trace -e *chdir -o /tmp/bla perf report --ignore-vmlinux -i ../perf.data

The perf_mmap__consume() could unmap the mmap. It needs to check the
refcnt in perf_mmap__read_done().

Reported-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Wang Nan <wangnan0@huawei.com>
Fixes: ee023de05f35 ("perf mmap: Introduce perf_mmap__read_done()")
Link: http://lkml.kernel.org/r/1522071729-16776-1-git-send-email-kan.liang@linux.intel.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/util/mmap.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/tools/perf/util/mmap.c b/tools/perf/util/mmap.c
index 38ca3ffb9d61..f6cfc52ff1fe 100644
--- a/tools/perf/util/mmap.c
+++ b/tools/perf/util/mmap.c
@@ -317,5 +317,11 @@ int perf_mmap__push(struct perf_mmap *md, void *to,
  */
 void perf_mmap__read_done(struct perf_mmap *map)
 {
+	/*
+	 * Check if event was unmapped due to a POLLHUP/POLLERR.
+	 */
+	if (!refcount_read(&map->refcnt))
+		return;
+
 	map->prev = perf_mmap__read_head(map);
 }
-- 
2.14.3

[PATCH 3/8] perf mmap: Be consistent when checking for an unmaped ring buffer

[Arnaldo Carvalho de Melo]

From: Arnaldo Carvalho de Melo <acme@redhat.com>

The previous patch is insufficient to cure the reported 'perf trace'
segfault, as it only cures the perf_mmap__read_done() case, moving the
segfault to perf_mmap__read_init() functio, fix it by doing the same
refcount check.

Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: David Ahern <dsahern@gmail.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Kan Liang <kan.liang@intel.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Wang Nan <wangnan0@huawei.com>
Fixes: 8872481bd048 ("perf mmap: Introduce perf_mmap__read_init()")
Link: https://lkml.kernel.org/r/20180326144127.GF18897@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/util/mmap.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/tools/perf/util/mmap.c b/tools/perf/util/mmap.c
index f6cfc52ff1fe..fc832676a798 100644
--- a/tools/perf/util/mmap.c
+++ b/tools/perf/util/mmap.c
@@ -234,7 +234,7 @@ static int overwrite_rb_find_range(void *buf, int mask, u64 *start, u64 *end)
 /*
  * Report the start and end of the available data in ringbuffer
  */
-int perf_mmap__read_init(struct perf_mmap *md)
+static int __perf_mmap__read_init(struct perf_mmap *md)
 {
 	u64 head = perf_mmap__read_head(md);
 	u64 old = md->prev;
@@ -268,6 +268,17 @@ int perf_mmap__read_init(struct perf_mmap *md)
 	return 0;
 }
 
+int perf_mmap__read_init(struct perf_mmap *map)
+{
+	/*
+	 * Check if event was unmapped due to a POLLHUP/POLLERR.
+	 */
+	if (!refcount_read(&map->refcnt))
+		return -ENOENT;
+
+	return __perf_mmap__read_init(map);
+}
+
 int perf_mmap__push(struct perf_mmap *md, void *to,
 		    int push(void *to, void *buf, size_t size))
 {
-- 
2.14.3

[PATCH 4/8] perf vendor events s390: Add JSON files for IBM z10EC z10BC

[Arnaldo Carvalho de Melo]

From: Thomas Richter <tmricht@linux.vnet.ibm.com>

Add CPU measurement counter facility event description files (JSON
files) for IBM z10EC and z10BC.

Signed-off-by: Thomas Richter <tmricht@linux.vnet.ibm.com>
Reviewed-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Link: http://lkml.kernel.org/r/20180326082538.2258-1-tmricht@linux.vnet.ibm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/pmu-events/arch/s390/cf_z10/basic.json  |  74 ++++++++++++++
 tools/perf/pmu-events/arch/s390/cf_z10/crypto.json |  98 ++++++++++++++++++
 .../perf/pmu-events/arch/s390/cf_z10/extended.json | 110 +++++++++++++++++++++
 tools/perf/pmu-events/arch/s390/mapfile.csv        |   2 +
 4 files changed, 284 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/s390/cf_z10/basic.json
 create mode 100644 tools/perf/pmu-events/arch/s390/cf_z10/crypto.json
 create mode 100644 tools/perf/pmu-events/arch/s390/cf_z10/extended.json
 create mode 100644 tools/perf/pmu-events/arch/s390/mapfile.csv

diff --git a/tools/perf/pmu-events/arch/s390/cf_z10/basic.json b/tools/perf/pmu-events/arch/s390/cf_z10/basic.json
new file mode 100644
index 000000000000..8bf16759ca53
--- /dev/null
+++ b/tools/perf/pmu-events/arch/s390/cf_z10/basic.json
@@ -0,0 +1,74 @@
+[
+	{
+		"EventCode": "0",
+		"EventName": "CPU_CYCLES",
+		"BriefDescription": "CPU Cycles",
+		"PublicDescription": "Cycle Count"
+	},
+	{
+		"EventCode": "1",
+		"EventName": "INSTRUCTIONS",
+		"BriefDescription": "Instructions",
+		"PublicDescription": "Instruction Count"
+	},
+	{
+		"EventCode": "2",
+		"EventName": "L1I_DIR_WRITES",
+		"BriefDescription": "L1I Directory Writes",
+		"PublicDescription": "Level-1 I-Cache Directory Write Count"
+	},
+	{
+		"EventCode": "3",
+		"EventName": "L1I_PENALTY_CYCLES",
+		"BriefDescription": "L1I Penalty Cycles",
+		"PublicDescription": "Level-1 I-Cache Penalty Cycle Count"
+	},
+	{
+		"EventCode": "4",
+		"EventName": "L1D_DIR_WRITES",
+		"BriefDescription": "L1D Directory Writes",
+		"PublicDescription": "Level-1 D-Cache Directory Write Count"
+	},
+	{
+		"EventCode": "5",
+		"EventName": "L1D_PENALTY_CYCLES",
+		"BriefDescription": "L1D Penalty Cycles",
+		"PublicDescription": "Level-1 D-Cache Penalty Cycle Count"
+	},
+	{
+		"EventCode": "32",
+		"EventName": "PROBLEM_STATE_CPU_CYCLES",
+		"BriefDescription": "Problem-State CPU Cycles",
+		"PublicDescription": "Problem-State Cycle Count"
+	},
+	{
+		"EventCode": "33",
+		"EventName": "PROBLEM_STATE_INSTRUCTIONS",
+		"BriefDescription": "Problem-State Instructions",
+		"PublicDescription": "Problem-State Instruction Count"
+	},
+	{
+		"EventCode": "34",
+		"EventName": "PROBLEM_STATE_L1I_DIR_WRITES",
+		"BriefDescription": "Problem-State L1I Directory Writes",
+		"PublicDescription": "Problem-State Level-1 I-Cache Directory Write Count"
+	},
+	{
+		"EventCode": "35",
+		"EventName": "PROBLEM_STATE_L1I_PENALTY_CYCLES",
+		"BriefDescription": "Problem-State L1I Penalty Cycles",
+		"PublicDescription": "Problem-State Level-1 I-Cache Penalty Cycle Count"
+	},
+	{
+		"EventCode": "36",
+		"EventName": "PROBLEM_STATE_L1D_DIR_WRITES",
+		"BriefDescription": "Problem-State L1D Directory Writes",
+		"PublicDescription": "Problem-State Level-1 D-Cache Directory Write Count"
+	},
+	{
+		"EventCode": "37",
+		"EventName": "PROBLEM_STATE_L1D_PENALTY_CYCLES",
+		"BriefDescription": "Problem-State L1D Penalty Cycles",
+		"PublicDescription": "Problem-State Level-1 D-Cache Penalty Cycle Count"
+	},
+]
diff --git a/tools/perf/pmu-events/arch/s390/cf_z10/crypto.json b/tools/perf/pmu-events/arch/s390/cf_z10/crypto.json
new file mode 100644
index 000000000000..7e5b72492141
--- /dev/null
+++ b/tools/perf/pmu-events/arch/s390/cf_z10/crypto.json
@@ -0,0 +1,98 @@
+[
+	{
+		"EventCode": "64",
+		"EventName": "PRNG_FUNCTIONS",
+		"BriefDescription": "PRNG Functions",
+		"PublicDescription": "Total number of the PRNG functions issued by the CPU"
+	},
+	{
+		"EventCode": "65",
+		"EventName": "PRNG_CYCLES",
+		"BriefDescription": "PRNG Cycles",
+		"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing PRNG functions issued by the CPU"
+	},
+	{
+		"EventCode": "66",
+		"EventName": "PRNG_BLOCKED_FUNCTIONS",
+		"BriefDescription": "PRNG Blocked Functions",
+		"PublicDescription": "Total number of the PRNG functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+	},
+	{
+		"EventCode": "67",
+		"EventName": "PRNG_BLOCKED_CYCLES",
+		"BriefDescription": "PRNG Blocked Cycles",
+		"PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+	},
+	{
+		"EventCode": "68",
+		"EventName": "SHA_FUNCTIONS",
+		"BriefDescription": "SHA Functions",
+		"PublicDescription": "Total number of SHA functions issued by the CPU"
+	},
+	{
+		"EventCode": "69",
+		"EventName": "SHA_CYCLES",
+		"BriefDescription": "SHA Cycles",
+		"PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU"
+	},
+	{
+		"EventCode": "70",
+		"EventName": "SHA_BLOCKED_FUNCTIONS",
+		"BriefDescription": "SHA Blocked Functions",
+		"PublicDescription": "Total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU"
+	},
+	{
+		"EventCode": "71",
+		"EventName": "SHA_BLOCKED_CYCLES",
+		"BriefDescription": "SHA Bloced Cycles",
+		"PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU"
+	},
+	{
+		"EventCode": "72",
+		"EventName": "DEA_FUNCTIONS",
+		"BriefDescription": "DEA Functions",
+		"PublicDescription": "Total number of the DEA functions issued by the CPU"
+	},
+	{
+		"EventCode": "73",
+		"EventName": "DEA_CYCLES",
+		"BriefDescription": "DEA Cycles",
+		"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU"
+	},
+	{
+		"EventCode": "74",
+		"EventName": "DEA_BLOCKED_FUNCTIONS",
+		"BriefDescription": "DEA Blocked Functions",
+		"PublicDescription": "Total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+	},
+	{
+		"EventCode": "75",
+		"EventName": "DEA_BLOCKED_CYCLES",
+		"BriefDescription": "DEA Blocked Cycles",
+		"PublicDescription": "Total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+	},
+	{
+		"EventCode": "76",
+		"EventName": "AES_FUNCTIONS",
+		"BriefDescription": "AES Functions",
+		"PublicDescription": "Total number of AES functions issued by the CPU"
+	},
+	{
+		"EventCode": "77",
+		"EventName": "AES_CYCLES",
+		"BriefDescription": "AES Cycles",
+		"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU"
+	},
+	{
+		"EventCode": "78",
+		"EventName": "AES_BLOCKED_FUNCTIONS",
+		"BriefDescription": "AES Blocked Functions",
+		"PublicDescription": "Total number of AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+	},
+	{
+		"EventCode": "79",
+		"EventName": "AES_BLOCKED_CYCLES",
+		"BriefDescription": "AES Blocked Cycles",
+		"PublicDescription": "Total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+	},
+]
diff --git a/tools/perf/pmu-events/arch/s390/cf_z10/extended.json b/tools/perf/pmu-events/arch/s390/cf_z10/extended.json
new file mode 100644
index 000000000000..0feedb40f30f
--- /dev/null
+++ b/tools/perf/pmu-events/arch/s390/cf_z10/extended.json
@@ -0,0 +1,110 @@
+[
+	{
+		"EventCode": "128",
+		"EventName": "L1I_L2_SOURCED_WRITES",
+		"BriefDescription": "L1I L2 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from the Level-2 (L1.5) cache"
+	},
+	{
+		"EventCode": "129",
+		"EventName": "L1D_L2_SOURCED_WRITES",
+		"BriefDescription": "L1D L2 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 D-Cache directory where the installed cache line was sourced from the Level-2 (L1.5) cache"
+	},
+	{
+		"EventCode": "130",
+		"EventName": "L1I_L3_LOCAL_WRITES",
+		"BriefDescription": "L1I L3 Local Writes",
+		"PublicDescription": "A directory write to the Level-1 I-Cache directory where the installed cache line was sourced from the Level-3 cache that is on the same book as the Instruction cache (Local L2 cache)"
+	},
+	{
+		"EventCode": "131",
+		"EventName": "L1D_L3_LOCAL_WRITES",
+		"BriefDescription": "L1D L3 Local Writes",
+		"PublicDescription": "A directory write to the Level-1 D-Cache directory where the installtion cache line was source from the Level-3 cache that is on the same book as the Data cache (Local L2 cache)"
+	},
+	{
+		"EventCode": "132",
+		"EventName": "L1I_L3_REMOTE_WRITES",
+		"BriefDescription": "L1I L3 Remote Writes",
+		"PublicDescription": "A directory write to the Level-1 I-Cache directory where the installed cache line was sourced from a Level-3 cache that is not on the same book as the Instruction cache (Remote L2 cache)"
+	},
+	{
+		"EventCode": "133",
+		"EventName": "L1D_L3_REMOTE_WRITES",
+		"BriefDescription": "L1D L3 Remote Writes",
+		"PublicDescription": "A directory write to the Level-1 D-Cache directory where the installed cache line was sourced from a Level-3 cache that is not on the same book as the Data cache (Remote L2 cache)"
+	},
+	{
+		"EventCode": "134",
+		"EventName": "L1D_LMEM_SOURCED_WRITES",
+		"BriefDescription": "L1D Local Memory Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 D-Cache directory where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)"
+	},
+	{
+		"EventCode": "135",
+		"EventName": "L1I_LMEM_SOURCED_WRITES",
+		"BriefDescription": "L1I Local Memory Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 I-Cache where the installed cache line was sourced from memory that is attached to the s ame book as the Instruction cache (Local Memory)"
+	},
+	{
+		"EventCode": "136",
+		"EventName": "L1D_RO_EXCL_WRITES",
+		"BriefDescription": "L1D Read-only Exclusive Writes",
+		"PublicDescription": "A directory write to the Level-1 D-Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line"
+	},
+	{
+		"EventCode": "137",
+		"EventName": "L1I_CACHELINE_INVALIDATES",
+		"BriefDescription": "L1I Cacheline Invalidates",
+		"PublicDescription": "A cache line in the Level-1 I-Cache has been invalidated by a store on the same CPU as the Level-1 I-Cache"
+	},
+	{
+		"EventCode": "138",
+		"EventName": "ITLB1_WRITES",
+		"BriefDescription": "ITLB1 Writes",
+		"PublicDescription": "A translation entry has been written into the Level-1 Instruction Translation Lookaside Buffer"
+	},
+	{
+		"EventCode": "139",
+		"EventName": "DTLB1_WRITES",
+		"BriefDescription": "DTLB1 Writes",
+		"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer"
+	},
+	{
+		"EventCode": "140",
+		"EventName": "TLB2_PTE_WRITES",
+		"BriefDescription": "TLB2 PTE Writes",
+		"PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays"
+	},
+	{
+		"EventCode": "141",
+		"EventName": "TLB2_CRSTE_WRITES",
+		"BriefDescription": "TLB2 CRSTE Writes",
+		"PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays"
+	},
+	{
+		"EventCode": "142",
+		"EventName": "TLB2_CRSTE_HPAGE_WRITES",
+		"BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes",
+		"PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation"
+	},
+	{
+		"EventCode": "145",
+		"EventName": "ITLB1_MISSES",
+		"BriefDescription": "ITLB1 Misses",
+		"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle an ITLB1 miss is in progress"
+	},
+	{
+		"EventCode": "146",
+		"EventName": "DTLB1_MISSES",
+		"BriefDescription": "DTLB1 Misses",
+		"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle an DTLB1 miss is in progress"
+	},
+	{
+		"EventCode": "147",
+		"EventName": "L2C_STORES_SENT",
+		"BriefDescription": "L2C Stores Sent",
+		"PublicDescription": "Incremented by one for every store sent to Level-2 (L1.5) cache"
+	},
+]
diff --git a/tools/perf/pmu-events/arch/s390/mapfile.csv b/tools/perf/pmu-events/arch/s390/mapfile.csv
new file mode 100644
index 000000000000..735159593c2c
--- /dev/null
+++ b/tools/perf/pmu-events/arch/s390/mapfile.csv
@@ -0,0 +1,2 @@
+Family-model,Version,Filename,EventType
+209[78],1,cf_z10,core
-- 
2.14.3

[PATCH 5/8] perf vendor events s390: Add JSON files for IBM z196

[Arnaldo Carvalho de Melo]

From: Thomas Richter <tmricht@linux.vnet.ibm.com>

Add CPU measurement counter facility event description files (json
files) for IBM z196.

Signed-off-by: Thomas Richter <tmricht@linux.vnet.ibm.com>
Reviewed-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Link: http://lkml.kernel.org/r/20180326082538.2258-2-tmricht@linux.vnet.ibm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/pmu-events/arch/s390/cf_z196/basic.json |  74 +++++++++++
 .../perf/pmu-events/arch/s390/cf_z196/crypto.json  |  98 ++++++++++++++
 .../pmu-events/arch/s390/cf_z196/extended.json     | 146 +++++++++++++++++++++
 tools/perf/pmu-events/arch/s390/mapfile.csv        |   1 +
 4 files changed, 319 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/s390/cf_z196/basic.json
 create mode 100644 tools/perf/pmu-events/arch/s390/cf_z196/crypto.json
 create mode 100644 tools/perf/pmu-events/arch/s390/cf_z196/extended.json

diff --git a/tools/perf/pmu-events/arch/s390/cf_z196/basic.json b/tools/perf/pmu-events/arch/s390/cf_z196/basic.json
new file mode 100644
index 000000000000..8bf16759ca53
--- /dev/null
+++ b/tools/perf/pmu-events/arch/s390/cf_z196/basic.json
@@ -0,0 +1,74 @@
+[
+	{
+		"EventCode": "0",
+		"EventName": "CPU_CYCLES",
+		"BriefDescription": "CPU Cycles",
+		"PublicDescription": "Cycle Count"
+	},
+	{
+		"EventCode": "1",
+		"EventName": "INSTRUCTIONS",
+		"BriefDescription": "Instructions",
+		"PublicDescription": "Instruction Count"
+	},
+	{
+		"EventCode": "2",
+		"EventName": "L1I_DIR_WRITES",
+		"BriefDescription": "L1I Directory Writes",
+		"PublicDescription": "Level-1 I-Cache Directory Write Count"
+	},
+	{
+		"EventCode": "3",
+		"EventName": "L1I_PENALTY_CYCLES",
+		"BriefDescription": "L1I Penalty Cycles",
+		"PublicDescription": "Level-1 I-Cache Penalty Cycle Count"
+	},
+	{
+		"EventCode": "4",
+		"EventName": "L1D_DIR_WRITES",
+		"BriefDescription": "L1D Directory Writes",
+		"PublicDescription": "Level-1 D-Cache Directory Write Count"
+	},
+	{
+		"EventCode": "5",
+		"EventName": "L1D_PENALTY_CYCLES",
+		"BriefDescription": "L1D Penalty Cycles",
+		"PublicDescription": "Level-1 D-Cache Penalty Cycle Count"
+	},
+	{
+		"EventCode": "32",
+		"EventName": "PROBLEM_STATE_CPU_CYCLES",
+		"BriefDescription": "Problem-State CPU Cycles",
+		"PublicDescription": "Problem-State Cycle Count"
+	},
+	{
+		"EventCode": "33",
+		"EventName": "PROBLEM_STATE_INSTRUCTIONS",
+		"BriefDescription": "Problem-State Instructions",
+		"PublicDescription": "Problem-State Instruction Count"
+	},
+	{
+		"EventCode": "34",
+		"EventName": "PROBLEM_STATE_L1I_DIR_WRITES",
+		"BriefDescription": "Problem-State L1I Directory Writes",
+		"PublicDescription": "Problem-State Level-1 I-Cache Directory Write Count"
+	},
+	{
+		"EventCode": "35",
+		"EventName": "PROBLEM_STATE_L1I_PENALTY_CYCLES",
+		"BriefDescription": "Problem-State L1I Penalty Cycles",
+		"PublicDescription": "Problem-State Level-1 I-Cache Penalty Cycle Count"
+	},
+	{
+		"EventCode": "36",
+		"EventName": "PROBLEM_STATE_L1D_DIR_WRITES",
+		"BriefDescription": "Problem-State L1D Directory Writes",
+		"PublicDescription": "Problem-State Level-1 D-Cache Directory Write Count"
+	},
+	{
+		"EventCode": "37",
+		"EventName": "PROBLEM_STATE_L1D_PENALTY_CYCLES",
+		"BriefDescription": "Problem-State L1D Penalty Cycles",
+		"PublicDescription": "Problem-State Level-1 D-Cache Penalty Cycle Count"
+	},
+]
diff --git a/tools/perf/pmu-events/arch/s390/cf_z196/crypto.json b/tools/perf/pmu-events/arch/s390/cf_z196/crypto.json
new file mode 100644
index 000000000000..7e5b72492141
--- /dev/null
+++ b/tools/perf/pmu-events/arch/s390/cf_z196/crypto.json
@@ -0,0 +1,98 @@
+[
+	{
+		"EventCode": "64",
+		"EventName": "PRNG_FUNCTIONS",
+		"BriefDescription": "PRNG Functions",
+		"PublicDescription": "Total number of the PRNG functions issued by the CPU"
+	},
+	{
+		"EventCode": "65",
+		"EventName": "PRNG_CYCLES",
+		"BriefDescription": "PRNG Cycles",
+		"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing PRNG functions issued by the CPU"
+	},
+	{
+		"EventCode": "66",
+		"EventName": "PRNG_BLOCKED_FUNCTIONS",
+		"BriefDescription": "PRNG Blocked Functions",
+		"PublicDescription": "Total number of the PRNG functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+	},
+	{
+		"EventCode": "67",
+		"EventName": "PRNG_BLOCKED_CYCLES",
+		"BriefDescription": "PRNG Blocked Cycles",
+		"PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+	},
+	{
+		"EventCode": "68",
+		"EventName": "SHA_FUNCTIONS",
+		"BriefDescription": "SHA Functions",
+		"PublicDescription": "Total number of SHA functions issued by the CPU"
+	},
+	{
+		"EventCode": "69",
+		"EventName": "SHA_CYCLES",
+		"BriefDescription": "SHA Cycles",
+		"PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU"
+	},
+	{
+		"EventCode": "70",
+		"EventName": "SHA_BLOCKED_FUNCTIONS",
+		"BriefDescription": "SHA Blocked Functions",
+		"PublicDescription": "Total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU"
+	},
+	{
+		"EventCode": "71",
+		"EventName": "SHA_BLOCKED_CYCLES",
+		"BriefDescription": "SHA Bloced Cycles",
+		"PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU"
+	},
+	{
+		"EventCode": "72",
+		"EventName": "DEA_FUNCTIONS",
+		"BriefDescription": "DEA Functions",
+		"PublicDescription": "Total number of the DEA functions issued by the CPU"
+	},
+	{
+		"EventCode": "73",
+		"EventName": "DEA_CYCLES",
+		"BriefDescription": "DEA Cycles",
+		"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU"
+	},
+	{
+		"EventCode": "74",
+		"EventName": "DEA_BLOCKED_FUNCTIONS",
+		"BriefDescription": "DEA Blocked Functions",
+		"PublicDescription": "Total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+	},
+	{
+		"EventCode": "75",
+		"EventName": "DEA_BLOCKED_CYCLES",
+		"BriefDescription": "DEA Blocked Cycles",
+		"PublicDescription": "Total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+	},
+	{
+		"EventCode": "76",
+		"EventName": "AES_FUNCTIONS",
+		"BriefDescription": "AES Functions",
+		"PublicDescription": "Total number of AES functions issued by the CPU"
+	},
+	{
+		"EventCode": "77",
+		"EventName": "AES_CYCLES",
+		"BriefDescription": "AES Cycles",
+		"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU"
+	},
+	{
+		"EventCode": "78",
+		"EventName": "AES_BLOCKED_FUNCTIONS",
+		"BriefDescription": "AES Blocked Functions",
+		"PublicDescription": "Total number of AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+	},
+	{
+		"EventCode": "79",
+		"EventName": "AES_BLOCKED_CYCLES",
+		"BriefDescription": "AES Blocked Cycles",
+		"PublicDescription": "Total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+	},
+]
diff --git a/tools/perf/pmu-events/arch/s390/cf_z196/extended.json b/tools/perf/pmu-events/arch/s390/cf_z196/extended.json
new file mode 100644
index 000000000000..b6d7fec7c2e7
--- /dev/null
+++ b/tools/perf/pmu-events/arch/s390/cf_z196/extended.json
@@ -0,0 +1,146 @@
+[
+	{
+		"EventCode": "128",
+		"EventName": "L1D_L2_SOURCED_WRITES",
+		"BriefDescription": "L1D L2 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from the Level-2 cache"
+	},
+	{
+		"EventCode": "129",
+		"EventName": "L1I_L2_SOURCED_WRITES",
+		"BriefDescription": "L1I L2 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from the Level-2 cache"
+	},
+	{
+		"EventCode": "130",
+		"EventName": "DTLB1_MISSES",
+		"BriefDescription": "DTLB1 Misses",
+		"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB1 miss is in progress."
+	},
+	{
+		"EventCode": "131",
+		"EventName": "ITLB1_MISSES",
+		"BriefDescription": "ITLB1 Misses",
+		"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle a ITLB1 miss is in progress."
+	},
+	{
+		"EventCode": "133",
+		"EventName": "L2C_STORES_SENT",
+		"BriefDescription": "L2C Stores Sent",
+		"PublicDescription": "Incremented by one for every store sent to Level-2 cache"
+	},
+	{
+		"EventCode": "134",
+		"EventName": "L1D_OFFBOOK_L3_SOURCED_WRITES",
+		"BriefDescription": "L1D Off-Book L3 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from an Off Book Level-3 cache"
+	},
+	{
+		"EventCode": "135",
+		"EventName": "L1D_ONBOOK_L4_SOURCED_WRITES",
+		"BriefDescription": "L1D On-Book L4 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from an On Book Level-4 cache"
+	},
+	{
+		"EventCode": "136",
+		"EventName": "L1I_ONBOOK_L4_SOURCED_WRITES",
+		"BriefDescription": "L1I On-Book L4 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from an On Book Level-4 cache"
+	},
+	{
+		"EventCode": "137",
+		"EventName": "L1D_RO_EXCL_WRITES",
+		"BriefDescription": "L1D Read-only Exclusive Writes",
+		"PublicDescription": "A directory write to the Level-1 D-Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line"
+	},
+	{
+		"EventCode": "138",
+		"EventName": "L1D_OFFBOOK_L4_SOURCED_WRITES",
+		"BriefDescription": "L1D Off-Book L4 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from an Off Book Level-4 cache"
+	},
+	{
+		"EventCode": "139",
+		"EventName": "L1I_OFFBOOK_L4_SOURCED_WRITES",
+		"BriefDescription": "L1I Off-Book L4 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from an Off Book Level-4 cache"
+	},
+	{
+		"EventCode": "140",
+		"EventName": "DTLB1_HPAGE_WRITES",
+		"BriefDescription": "DTLB1 One-Megabyte Page Writes",
+		"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page"
+	},
+	{
+		"EventCode": "141",
+		"EventName": "L1D_LMEM_SOURCED_WRITES",
+		"BriefDescription": "L1D Local Memory Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 D-Cache where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)"
+	},
+	{
+		"EventCode": "142",
+		"EventName": "L1I_LMEM_SOURCED_WRITES",
+		"BriefDescription": "L1I Local Memory Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 I-Cache where the installed cache line was sourced from memory that is attached to the same book as the Instruction cache (Local Memory)"
+	},
+	{
+		"EventCode": "143",
+		"EventName": "L1I_OFFBOOK_L3_SOURCED_WRITES",
+		"BriefDescription": "L1I Off-Book L3 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from an Off Book Level-3 cache"
+	},
+	{
+		"EventCode": "144",
+		"EventName": "DTLB1_WRITES",
+		"BriefDescription": "DTLB1 Writes",
+		"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer"
+	},
+	{
+		"EventCode": "145",
+		"EventName": "ITLB1_WRITES",
+		"BriefDescription": "ITLB1 Writes",
+		"PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation Lookaside Buffer"
+	},
+	{
+		"EventCode": "146",
+		"EventName": "TLB2_PTE_WRITES",
+		"BriefDescription": "TLB2 PTE Writes",
+		"PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays"
+	},
+	{
+		"EventCode": "147",
+		"EventName": "TLB2_CRSTE_HPAGE_WRITES",
+		"BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes",
+		"PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation"
+	},
+	{
+		"EventCode": "148",
+		"EventName": "TLB2_CRSTE_WRITES",
+		"BriefDescription": "TLB2 CRSTE Writes",
+		"PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays"
+	},
+	{
+		"EventCode": "150",
+		"EventName": "L1D_ONCHIP_L3_SOURCED_WRITES",
+		"BriefDescription": "L1D On-Chip L3 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from an On Chip Level-3 cache"
+	},
+	{
+		"EventCode": "152",
+		"EventName": "L1D_OFFCHIP_L3_SOURCED_WRITES",
+		"BriefDescription": "L1D Off-Chip L3 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache"
+	},
+	{
+		"EventCode": "153",
+		"EventName": "L1I_ONCHIP_L3_SOURCED_WRITES",
+		"BriefDescription": "L1I On-Chip L3 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from an On Chip Level-3 cache"
+	},
+	{
+		"EventCode": "155",
+		"EventName": "L1I_OFFCHIP_L3_SOURCED_WRITES",
+		"BriefDescription": "L1I Off-Chip L3 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache"
+	},
+]
diff --git a/tools/perf/pmu-events/arch/s390/mapfile.csv b/tools/perf/pmu-events/arch/s390/mapfile.csv
index 735159593c2c..b9c673087011 100644
--- a/tools/perf/pmu-events/arch/s390/mapfile.csv
+++ b/tools/perf/pmu-events/arch/s390/mapfile.csv
@@ -1,2 +1,3 @@
 Family-model,Version,Filename,EventType
 209[78],1,cf_z10,core
+281[78],1,cf_z196,core
-- 
2.14.3

[PATCH 6/8] perf vendor events s390: Add JSON files for IBM zEC12 zBC12

[Arnaldo Carvalho de Melo]

From: Thomas Richter <tmricht@linux.vnet.ibm.com>

Add CPU measurement counter facility event description files (json
files) for IBM zEC12 and zBC12.

Signed-off-by: Thomas Richter <tmricht@linux.vnet.ibm.com>
Reviewed-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Link: http://lkml.kernel.org/r/20180326082538.2258-3-tmricht@linux.vnet.ibm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 .../perf/pmu-events/arch/s390/cf_zec12/basic.json  |  74 +++++++
 .../perf/pmu-events/arch/s390/cf_zec12/crypto.json |  98 ++++++++++
 .../pmu-events/arch/s390/cf_zec12/extended.json    | 212 +++++++++++++++++++++
 tools/perf/pmu-events/arch/s390/mapfile.csv        |   1 +
 4 files changed, 385 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/s390/cf_zec12/basic.json
 create mode 100644 tools/perf/pmu-events/arch/s390/cf_zec12/crypto.json
 create mode 100644 tools/perf/pmu-events/arch/s390/cf_zec12/extended.json

diff --git a/tools/perf/pmu-events/arch/s390/cf_zec12/basic.json b/tools/perf/pmu-events/arch/s390/cf_zec12/basic.json
new file mode 100644
index 000000000000..8bf16759ca53
--- /dev/null
+++ b/tools/perf/pmu-events/arch/s390/cf_zec12/basic.json
@@ -0,0 +1,74 @@
+[
+	{
+		"EventCode": "0",
+		"EventName": "CPU_CYCLES",
+		"BriefDescription": "CPU Cycles",
+		"PublicDescription": "Cycle Count"
+	},
+	{
+		"EventCode": "1",
+		"EventName": "INSTRUCTIONS",
+		"BriefDescription": "Instructions",
+		"PublicDescription": "Instruction Count"
+	},
+	{
+		"EventCode": "2",
+		"EventName": "L1I_DIR_WRITES",
+		"BriefDescription": "L1I Directory Writes",
+		"PublicDescription": "Level-1 I-Cache Directory Write Count"
+	},
+	{
+		"EventCode": "3",
+		"EventName": "L1I_PENALTY_CYCLES",
+		"BriefDescription": "L1I Penalty Cycles",
+		"PublicDescription": "Level-1 I-Cache Penalty Cycle Count"
+	},
+	{
+		"EventCode": "4",
+		"EventName": "L1D_DIR_WRITES",
+		"BriefDescription": "L1D Directory Writes",
+		"PublicDescription": "Level-1 D-Cache Directory Write Count"
+	},
+	{
+		"EventCode": "5",
+		"EventName": "L1D_PENALTY_CYCLES",
+		"BriefDescription": "L1D Penalty Cycles",
+		"PublicDescription": "Level-1 D-Cache Penalty Cycle Count"
+	},
+	{
+		"EventCode": "32",
+		"EventName": "PROBLEM_STATE_CPU_CYCLES",
+		"BriefDescription": "Problem-State CPU Cycles",
+		"PublicDescription": "Problem-State Cycle Count"
+	},
+	{
+		"EventCode": "33",
+		"EventName": "PROBLEM_STATE_INSTRUCTIONS",
+		"BriefDescription": "Problem-State Instructions",
+		"PublicDescription": "Problem-State Instruction Count"
+	},
+	{
+		"EventCode": "34",
+		"EventName": "PROBLEM_STATE_L1I_DIR_WRITES",
+		"BriefDescription": "Problem-State L1I Directory Writes",
+		"PublicDescription": "Problem-State Level-1 I-Cache Directory Write Count"
+	},
+	{
+		"EventCode": "35",
+		"EventName": "PROBLEM_STATE_L1I_PENALTY_CYCLES",
+		"BriefDescription": "Problem-State L1I Penalty Cycles",
+		"PublicDescription": "Problem-State Level-1 I-Cache Penalty Cycle Count"
+	},
+	{
+		"EventCode": "36",
+		"EventName": "PROBLEM_STATE_L1D_DIR_WRITES",
+		"BriefDescription": "Problem-State L1D Directory Writes",
+		"PublicDescription": "Problem-State Level-1 D-Cache Directory Write Count"
+	},
+	{
+		"EventCode": "37",
+		"EventName": "PROBLEM_STATE_L1D_PENALTY_CYCLES",
+		"BriefDescription": "Problem-State L1D Penalty Cycles",
+		"PublicDescription": "Problem-State Level-1 D-Cache Penalty Cycle Count"
+	},
+]
diff --git a/tools/perf/pmu-events/arch/s390/cf_zec12/crypto.json b/tools/perf/pmu-events/arch/s390/cf_zec12/crypto.json
new file mode 100644
index 000000000000..7e5b72492141
--- /dev/null
+++ b/tools/perf/pmu-events/arch/s390/cf_zec12/crypto.json
@@ -0,0 +1,98 @@
+[
+	{
+		"EventCode": "64",
+		"EventName": "PRNG_FUNCTIONS",
+		"BriefDescription": "PRNG Functions",
+		"PublicDescription": "Total number of the PRNG functions issued by the CPU"
+	},
+	{
+		"EventCode": "65",
+		"EventName": "PRNG_CYCLES",
+		"BriefDescription": "PRNG Cycles",
+		"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing PRNG functions issued by the CPU"
+	},
+	{
+		"EventCode": "66",
+		"EventName": "PRNG_BLOCKED_FUNCTIONS",
+		"BriefDescription": "PRNG Blocked Functions",
+		"PublicDescription": "Total number of the PRNG functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+	},
+	{
+		"EventCode": "67",
+		"EventName": "PRNG_BLOCKED_CYCLES",
+		"BriefDescription": "PRNG Blocked Cycles",
+		"PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+	},
+	{
+		"EventCode": "68",
+		"EventName": "SHA_FUNCTIONS",
+		"BriefDescription": "SHA Functions",
+		"PublicDescription": "Total number of SHA functions issued by the CPU"
+	},
+	{
+		"EventCode": "69",
+		"EventName": "SHA_CYCLES",
+		"BriefDescription": "SHA Cycles",
+		"PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU"
+	},
+	{
+		"EventCode": "70",
+		"EventName": "SHA_BLOCKED_FUNCTIONS",
+		"BriefDescription": "SHA Blocked Functions",
+		"PublicDescription": "Total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU"
+	},
+	{
+		"EventCode": "71",
+		"EventName": "SHA_BLOCKED_CYCLES",
+		"BriefDescription": "SHA Bloced Cycles",
+		"PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU"
+	},
+	{
+		"EventCode": "72",
+		"EventName": "DEA_FUNCTIONS",
+		"BriefDescription": "DEA Functions",
+		"PublicDescription": "Total number of the DEA functions issued by the CPU"
+	},
+	{
+		"EventCode": "73",
+		"EventName": "DEA_CYCLES",
+		"BriefDescription": "DEA Cycles",
+		"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU"
+	},
+	{
+		"EventCode": "74",
+		"EventName": "DEA_BLOCKED_FUNCTIONS",
+		"BriefDescription": "DEA Blocked Functions",
+		"PublicDescription": "Total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+	},
+	{
+		"EventCode": "75",
+		"EventName": "DEA_BLOCKED_CYCLES",
+		"BriefDescription": "DEA Blocked Cycles",
+		"PublicDescription": "Total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+	},
+	{
+		"EventCode": "76",
+		"EventName": "AES_FUNCTIONS",
+		"BriefDescription": "AES Functions",
+		"PublicDescription": "Total number of AES functions issued by the CPU"
+	},
+	{
+		"EventCode": "77",
+		"EventName": "AES_CYCLES",
+		"BriefDescription": "AES Cycles",
+		"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU"
+	},
+	{
+		"EventCode": "78",
+		"EventName": "AES_BLOCKED_FUNCTIONS",
+		"BriefDescription": "AES Blocked Functions",
+		"PublicDescription": "Total number of AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+	},
+	{
+		"EventCode": "79",
+		"EventName": "AES_BLOCKED_CYCLES",
+		"BriefDescription": "AES Blocked Cycles",
+		"PublicDescription": "Total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+	},
+]
diff --git a/tools/perf/pmu-events/arch/s390/cf_zec12/extended.json b/tools/perf/pmu-events/arch/s390/cf_zec12/extended.json
new file mode 100644
index 000000000000..8682126aabb2
--- /dev/null
+++ b/tools/perf/pmu-events/arch/s390/cf_zec12/extended.json
@@ -0,0 +1,212 @@
+[
+	{
+		"EventCode": "128",
+		"EventName": "DTLB1_MISSES",
+		"BriefDescription": "DTLB1 Misses",
+		"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB1 miss is in progress."
+	},
+	{
+		"EventCode": "129",
+		"EventName": "ITLB1_MISSES",
+		"BriefDescription": "ITLB1 Misses",
+		"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle a ITLB1 miss is in progress."
+	},
+	{
+		"EventCode": "130",
+		"EventName": "L1D_L2I_SOURCED_WRITES",
+		"BriefDescription": "L1D L2I Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Instruction cache"
+	},
+	{
+		"EventCode": "131",
+		"EventName": "L1I_L2I_SOURCED_WRITES",
+		"BriefDescription": "L1I L2I Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache"
+	},
+	{
+		"EventCode": "132",
+		"EventName": "L1D_L2D_SOURCED_WRITES",
+		"BriefDescription": "L1D L2D Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache"
+	},
+	{
+		"EventCode": "133",
+		"EventName": "DTLB1_WRITES",
+		"BriefDescription": "DTLB1 Writes",
+		"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer"
+	},
+	{
+		"EventCode": "135",
+		"EventName": "L1D_LMEM_SOURCED_WRITES",
+		"BriefDescription": "L1D Local Memory Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Data cache where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)"
+	},
+	{
+		"EventCode": "137",
+		"EventName": "L1I_LMEM_SOURCED_WRITES",
+		"BriefDescription": "L1I Local Memory Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache where the installed cache line was sourced from memory that is attached to the same book as the Instruction cache (Local Memory)"
+	},
+	{
+		"EventCode": "138",
+		"EventName": "L1D_RO_EXCL_WRITES",
+		"BriefDescription": "L1D Read-only Exclusive Writes",
+		"PublicDescription": "A directory write to the Level-1 D-Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line"
+	},
+	{
+		"EventCode": "139",
+		"EventName": "DTLB1_HPAGE_WRITES",
+		"BriefDescription": "DTLB1 One-Megabyte Page Writes",
+		"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page"
+	},
+	{
+		"EventCode": "140",
+		"EventName": "ITLB1_WRITES",
+		"BriefDescription": "ITLB1 Writes",
+		"PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation Lookaside Buffer"
+	},
+	{
+		"EventCode": "141",
+		"EventName": "TLB2_PTE_WRITES",
+		"BriefDescription": "TLB2 PTE Writes",
+		"PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays"
+	},
+	{
+		"EventCode": "142",
+		"EventName": "TLB2_CRSTE_HPAGE_WRITES",
+		"BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes",
+		"PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation"
+	},
+	{
+		"EventCode": "143",
+		"EventName": "TLB2_CRSTE_WRITES",
+		"BriefDescription": "TLB2 CRSTE Writes",
+		"PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays"
+	},
+	{
+		"EventCode": "144",
+		"EventName": "L1D_ONCHIP_L3_SOURCED_WRITES",
+		"BriefDescription": "L1D On-Chip L3 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On Chip Level-3 cache without intervention"
+	},
+	{
+		"EventCode": "145",
+		"EventName": "L1D_OFFCHIP_L3_SOURCED_WRITES",
+		"BriefDescription": "L1D Off-Chip L3 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache without intervention"
+	},
+	{
+		"EventCode": "146",
+		"EventName": "L1D_OFFBOOK_L3_SOURCED_WRITES",
+		"BriefDescription": "L1D Off-Book L3 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-3 cache without intervention"
+	},
+	{
+		"EventCode": "147",
+		"EventName": "L1D_ONBOOK_L4_SOURCED_WRITES",
+		"BriefDescription": "L1D On-Book L4 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On Book Level-4 cache"
+	},
+	{
+		"EventCode": "148",
+		"EventName": "L1D_OFFBOOK_L4_SOURCED_WRITES",
+		"BriefDescription": "L1D Off-Book L4 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-4 cache"
+	},
+	{
+		"EventCode": "149",
+		"EventName": "TX_NC_TEND",
+		"BriefDescription": "Completed TEND instructions in non-constrained TX mode",
+		"PublicDescription": "A TEND instruction has completed in a nonconstrained transactional-execution mode"
+	},
+	{
+		"EventCode": "150",
+		"EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_IV",
+		"BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from a On Chip Level-3 cache with intervention"
+	},
+	{
+		"EventCode": "151",
+		"EventName": "L1D_OFFCHIP_L3_SOURCED_WRITES_IV",
+		"BriefDescription": "L1D Off-Chip L3 Sourced Writes with Intervention",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache with intervention"
+	},
+	{
+		"EventCode": "152",
+		"EventName": "L1D_OFFBOOK_L3_SOURCED_WRITES_IV",
+		"BriefDescription": "L1D Off-Book L3 Sourced Writes with Intervention",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-3 cache with intervention"
+	},
+	{
+		"EventCode": "153",
+		"EventName": "L1I_ONCHIP_L3_SOURCED_WRITES",
+		"BriefDescription": "L1I On-Chip L3 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache without intervention"
+	},
+	{
+		"EventCode": "154",
+		"EventName": "L1I_OFFCHIP_L3_SOURCED_WRITES",
+		"BriefDescription": "L1I Off-Chip L3 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache without intervention"
+	},
+	{
+		"EventCode": "155",
+		"EventName": "L1I_OFFBOOK_L3_SOURCED_WRITES",
+		"BriefDescription": "L1I Off-Book L3 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-3 cache without intervention"
+	},
+	{
+		"EventCode": "156",
+		"EventName": "L1I_ONBOOK_L4_SOURCED_WRITES",
+		"BriefDescription": "L1I On-Book L4 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Book Level-4 cache"
+	},
+	{
+		"EventCode": "157",
+		"EventName": "L1I_OFFBOOK_L4_SOURCED_WRITES",
+		"BriefDescription": "L1I Off-Book L4 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-4 cache"
+	},
+	{
+		"EventCode": "158",
+		"EventName": "TX_C_TEND",
+		"BriefDescription": "Completed TEND instructions in constrained TX mode",
+		"PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode"
+	},
+	{
+		"EventCode": "159",
+		"EventName": "L1I_ONCHIP_L3_SOURCED_WRITES_IV",
+		"BriefDescription": "L1I On-Chip L3 Sourced Writes with Intervention",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache with intervention"
+	},
+	{
+		"EventCode": "160",
+		"EventName": "L1I_OFFCHIP_L3_SOURCED_WRITES_IV",
+		"BriefDescription": "L1I Off-Chip L3 Sourced Writes with Intervention",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache with intervention"
+	},
+	{
+		"EventCode": "161",
+		"EventName": "L1I_OFFBOOK_L3_SOURCED_WRITES_IV",
+		"BriefDescription": "L1I Off-Book L3 Sourced Writes with Intervention",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-3 cache with intervention"
+	},
+	{
+		"EventCode": "177",
+		"EventName": "TX_NC_TABORT",
+		"BriefDescription": "Aborted transactions in non-constrained TX mode",
+		"PublicDescription": "A transaction abort has occurred in a nonconstrained transactional-execution mode"
+	},
+	{
+		"EventCode": "178",
+		"EventName": "TX_C_TABORT_NO_SPECIAL",
+		"BriefDescription": "Aborted transactions in constrained TX mode not using special completion logic",
+		"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete"
+	},
+	{
+		"EventCode": "179",
+		"EventName": "TX_C_TABORT_SPECIAL",
+		"BriefDescription": "Aborted transactions in constrained TX mode using special completion logic",
+		"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete"
+	},
+]
diff --git a/tools/perf/pmu-events/arch/s390/mapfile.csv b/tools/perf/pmu-events/arch/s390/mapfile.csv
index b9c673087011..c57f8e75fa23 100644
--- a/tools/perf/pmu-events/arch/s390/mapfile.csv
+++ b/tools/perf/pmu-events/arch/s390/mapfile.csv
@@ -1,3 +1,4 @@
 Family-model,Version,Filename,EventType
 209[78],1,cf_z10,core
 281[78],1,cf_z196,core
+282[78],1,cf_zec12,core
-- 
2.14.3

[PATCH 7/8] perf vendor events s390: Add JSON files for IBM z13

[Arnaldo Carvalho de Melo]

From: Thomas Richter <tmricht@linux.vnet.ibm.com>

Add CPU measurement counter facility event description files (json
files) for IBM z13.

Signed-off-by: Thomas Richter <tmricht@linux.vnet.ibm.com>
Reviewed-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Link: http://lkml.kernel.org/r/20180326082538.2258-4-tmricht@linux.vnet.ibm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/pmu-events/arch/s390/cf_z13/basic.json  |  74 +++++
 tools/perf/pmu-events/arch/s390/cf_z13/crypto.json |  98 ++++++
 .../perf/pmu-events/arch/s390/cf_z13/extended.json | 338 +++++++++++++++++++++
 tools/perf/pmu-events/arch/s390/mapfile.csv        |   1 +
 4 files changed, 511 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/s390/cf_z13/basic.json
 create mode 100644 tools/perf/pmu-events/arch/s390/cf_z13/crypto.json
 create mode 100644 tools/perf/pmu-events/arch/s390/cf_z13/extended.json

diff --git a/tools/perf/pmu-events/arch/s390/cf_z13/basic.json b/tools/perf/pmu-events/arch/s390/cf_z13/basic.json
new file mode 100644
index 000000000000..8bf16759ca53
--- /dev/null
+++ b/tools/perf/pmu-events/arch/s390/cf_z13/basic.json
@@ -0,0 +1,74 @@
+[
+	{
+		"EventCode": "0",
+		"EventName": "CPU_CYCLES",
+		"BriefDescription": "CPU Cycles",
+		"PublicDescription": "Cycle Count"
+	},
+	{
+		"EventCode": "1",
+		"EventName": "INSTRUCTIONS",
+		"BriefDescription": "Instructions",
+		"PublicDescription": "Instruction Count"
+	},
+	{
+		"EventCode": "2",
+		"EventName": "L1I_DIR_WRITES",
+		"BriefDescription": "L1I Directory Writes",
+		"PublicDescription": "Level-1 I-Cache Directory Write Count"
+	},
+	{
+		"EventCode": "3",
+		"EventName": "L1I_PENALTY_CYCLES",
+		"BriefDescription": "L1I Penalty Cycles",
+		"PublicDescription": "Level-1 I-Cache Penalty Cycle Count"
+	},
+	{
+		"EventCode": "4",
+		"EventName": "L1D_DIR_WRITES",
+		"BriefDescription": "L1D Directory Writes",
+		"PublicDescription": "Level-1 D-Cache Directory Write Count"
+	},
+	{
+		"EventCode": "5",
+		"EventName": "L1D_PENALTY_CYCLES",
+		"BriefDescription": "L1D Penalty Cycles",
+		"PublicDescription": "Level-1 D-Cache Penalty Cycle Count"
+	},
+	{
+		"EventCode": "32",
+		"EventName": "PROBLEM_STATE_CPU_CYCLES",
+		"BriefDescription": "Problem-State CPU Cycles",
+		"PublicDescription": "Problem-State Cycle Count"
+	},
+	{
+		"EventCode": "33",
+		"EventName": "PROBLEM_STATE_INSTRUCTIONS",
+		"BriefDescription": "Problem-State Instructions",
+		"PublicDescription": "Problem-State Instruction Count"
+	},
+	{
+		"EventCode": "34",
+		"EventName": "PROBLEM_STATE_L1I_DIR_WRITES",
+		"BriefDescription": "Problem-State L1I Directory Writes",
+		"PublicDescription": "Problem-State Level-1 I-Cache Directory Write Count"
+	},
+	{
+		"EventCode": "35",
+		"EventName": "PROBLEM_STATE_L1I_PENALTY_CYCLES",
+		"BriefDescription": "Problem-State L1I Penalty Cycles",
+		"PublicDescription": "Problem-State Level-1 I-Cache Penalty Cycle Count"
+	},
+	{
+		"EventCode": "36",
+		"EventName": "PROBLEM_STATE_L1D_DIR_WRITES",
+		"BriefDescription": "Problem-State L1D Directory Writes",
+		"PublicDescription": "Problem-State Level-1 D-Cache Directory Write Count"
+	},
+	{
+		"EventCode": "37",
+		"EventName": "PROBLEM_STATE_L1D_PENALTY_CYCLES",
+		"BriefDescription": "Problem-State L1D Penalty Cycles",
+		"PublicDescription": "Problem-State Level-1 D-Cache Penalty Cycle Count"
+	},
+]
diff --git a/tools/perf/pmu-events/arch/s390/cf_z13/crypto.json b/tools/perf/pmu-events/arch/s390/cf_z13/crypto.json
new file mode 100644
index 000000000000..7e5b72492141
--- /dev/null
+++ b/tools/perf/pmu-events/arch/s390/cf_z13/crypto.json
@@ -0,0 +1,98 @@
+[
+	{
+		"EventCode": "64",
+		"EventName": "PRNG_FUNCTIONS",
+		"BriefDescription": "PRNG Functions",
+		"PublicDescription": "Total number of the PRNG functions issued by the CPU"
+	},
+	{
+		"EventCode": "65",
+		"EventName": "PRNG_CYCLES",
+		"BriefDescription": "PRNG Cycles",
+		"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing PRNG functions issued by the CPU"
+	},
+	{
+		"EventCode": "66",
+		"EventName": "PRNG_BLOCKED_FUNCTIONS",
+		"BriefDescription": "PRNG Blocked Functions",
+		"PublicDescription": "Total number of the PRNG functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+	},
+	{
+		"EventCode": "67",
+		"EventName": "PRNG_BLOCKED_CYCLES",
+		"BriefDescription": "PRNG Blocked Cycles",
+		"PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+	},
+	{
+		"EventCode": "68",
+		"EventName": "SHA_FUNCTIONS",
+		"BriefDescription": "SHA Functions",
+		"PublicDescription": "Total number of SHA functions issued by the CPU"
+	},
+	{
+		"EventCode": "69",
+		"EventName": "SHA_CYCLES",
+		"BriefDescription": "SHA Cycles",
+		"PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU"
+	},
+	{
+		"EventCode": "70",
+		"EventName": "SHA_BLOCKED_FUNCTIONS",
+		"BriefDescription": "SHA Blocked Functions",
+		"PublicDescription": "Total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU"
+	},
+	{
+		"EventCode": "71",
+		"EventName": "SHA_BLOCKED_CYCLES",
+		"BriefDescription": "SHA Bloced Cycles",
+		"PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU"
+	},
+	{
+		"EventCode": "72",
+		"EventName": "DEA_FUNCTIONS",
+		"BriefDescription": "DEA Functions",
+		"PublicDescription": "Total number of the DEA functions issued by the CPU"
+	},
+	{
+		"EventCode": "73",
+		"EventName": "DEA_CYCLES",
+		"BriefDescription": "DEA Cycles",
+		"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU"
+	},
+	{
+		"EventCode": "74",
+		"EventName": "DEA_BLOCKED_FUNCTIONS",
+		"BriefDescription": "DEA Blocked Functions",
+		"PublicDescription": "Total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+	},
+	{
+		"EventCode": "75",
+		"EventName": "DEA_BLOCKED_CYCLES",
+		"BriefDescription": "DEA Blocked Cycles",
+		"PublicDescription": "Total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+	},
+	{
+		"EventCode": "76",
+		"EventName": "AES_FUNCTIONS",
+		"BriefDescription": "AES Functions",
+		"PublicDescription": "Total number of AES functions issued by the CPU"
+	},
+	{
+		"EventCode": "77",
+		"EventName": "AES_CYCLES",
+		"BriefDescription": "AES Cycles",
+		"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU"
+	},
+	{
+		"EventCode": "78",
+		"EventName": "AES_BLOCKED_FUNCTIONS",
+		"BriefDescription": "AES Blocked Functions",
+		"PublicDescription": "Total number of AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+	},
+	{
+		"EventCode": "79",
+		"EventName": "AES_BLOCKED_CYCLES",
+		"BriefDescription": "AES Blocked Cycles",
+		"PublicDescription": "Total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+	},
+]
diff --git a/tools/perf/pmu-events/arch/s390/cf_z13/extended.json b/tools/perf/pmu-events/arch/s390/cf_z13/extended.json
new file mode 100644
index 000000000000..9a002b6967f1
--- /dev/null
+++ b/tools/perf/pmu-events/arch/s390/cf_z13/extended.json
@@ -0,0 +1,338 @@
+[
+	{
+		"EventCode": "128",
+		"EventName": "L1D_RO_EXCL_WRITES",
+		"BriefDescription": "L1D Read-only Exclusive Writes",
+		"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line."
+	},
+	{
+		"EventCode": "129",
+		"EventName": "DTLB1_WRITES",
+		"BriefDescription": "DTLB1 Writes",
+		"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer"
+	},
+	{
+		"EventCode": "130",
+		"EventName": "DTLB1_MISSES",
+		"BriefDescription": "DTLB1 Misses",
+		"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB1 miss is in progress."
+	},
+	{
+		"EventCode": "131",
+		"EventName": "DTLB1_HPAGE_WRITES",
+		"BriefDescription": "DTLB1 One-Megabyte Page Writes",
+		"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page"
+	},
+	{
+		"EventCode": "132",
+		"EventName": "DTLB1_GPAGE_WRITES",
+		"BriefDescription": "DTLB1 Two-Gigabyte Page Writes",
+		"PublicDescription": "Counter:132	Name:DTLB1_GPAGE_WRITES A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a two-gigabyte page."
+	},
+	{
+		"EventCode": "133",
+		"EventName": "L1D_L2D_SOURCED_WRITES",
+		"BriefDescription": "L1D L2D Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache"
+	},
+	{
+		"EventCode": "134",
+		"EventName": "ITLB1_WRITES",
+		"BriefDescription": "ITLB1 Writes",
+		"PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation Lookaside Buffer"
+	},
+	{
+		"EventCode": "135",
+		"EventName": "ITLB1_MISSES",
+		"BriefDescription": "ITLB1 Misses",
+		"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle an ITLB1 miss is in progress"
+	},
+	{
+		"EventCode": "136",
+		"EventName": "L1I_L2I_SOURCED_WRITES",
+		"BriefDescription": "L1I L2I Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache"
+	},
+	{
+		"EventCode": "137",
+		"EventName": "TLB2_PTE_WRITES",
+		"BriefDescription": "TLB2 PTE Writes",
+		"PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays"
+	},
+	{
+		"EventCode": "138",
+		"EventName": "TLB2_CRSTE_HPAGE_WRITES",
+		"BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes",
+		"PublicDescription": "A translation entry has been written to the Level-2 TLB Combined Region Segment Table Entry arrays for a one-megabyte large page translation"
+	},
+	{
+		"EventCode": "139",
+		"EventName": "TLB2_CRSTE_WRITES",
+		"BriefDescription": "TLB2 CRSTE Writes",
+		"PublicDescription": "A translation entry has been written to the Level-2 TLB Combined Region Segment Table Entry arrays"
+	},
+	{
+		"EventCode": "140",
+		"EventName": "TX_C_TEND",
+		"BriefDescription": "Completed TEND instructions in constrained TX mode",
+		"PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode"
+	},
+	{
+		"EventCode": "141",
+		"EventName": "TX_NC_TEND",
+		"BriefDescription": "Completed TEND instructions in non-constrained TX mode",
+		"PublicDescription": "A TEND instruction has completed in a non-constrained transactional-execution mode"
+	},
+	{
+		"EventCode": "143",
+		"EventName": "L1C_TLB1_MISSES",
+		"BriefDescription": "L1C TLB1 Misses",
+		"PublicDescription": "Increments by one for any cycle where a Level-1 cache or Level-1 TLB miss is in progress."
+	},
+	{
+		"EventCode": "144",
+		"EventName": "L1D_ONCHIP_L3_SOURCED_WRITES",
+		"BriefDescription": "L1D On-Chip L3 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention"
+	},
+	{
+		"EventCode": "145",
+		"EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_IV",
+		"BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache with intervention"
+	},
+	{
+		"EventCode": "146",
+		"EventName": "L1D_ONNODE_L4_SOURCED_WRITES",
+		"BriefDescription": "L1D On-Node L4 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Node Level-4 cache"
+	},
+	{
+		"EventCode": "147",
+		"EventName": "L1D_ONNODE_L3_SOURCED_WRITES_IV",
+		"BriefDescription": "L1D On-Node L3 Sourced Writes with Intervention",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Node Level-3 cache with intervention"
+	},
+	{
+		"EventCode": "148",
+		"EventName": "L1D_ONNODE_L3_SOURCED_WRITES",
+		"BriefDescription": "L1D On-Node L3 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Node Level-3 cache without intervention"
+	},
+	{
+		"EventCode": "149",
+		"EventName": "L1D_ONDRAWER_L4_SOURCED_WRITES",
+		"BriefDescription": "L1D On-Drawer L4 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-4 cache"
+	},
+	{
+		"EventCode": "150",
+		"EventName": "L1D_ONDRAWER_L3_SOURCED_WRITES_IV",
+		"BriefDescription": "L1D On-Drawer L3 Sourced Writes with Intervention",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache with intervention"
+	},
+	{
+		"EventCode": "151",
+		"EventName": "L1D_ONDRAWER_L3_SOURCED_WRITES",
+		"BriefDescription": "L1D On-Drawer L3 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache without intervention"
+	},
+	{
+		"EventCode": "152",
+		"EventName": "L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES",
+		"BriefDescription": "L1D Off-Drawer Same-Column L4 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-4 cache"
+	},
+	{
+		"EventCode": "153",
+		"EventName": "L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV",
+		"BriefDescription": "L1D Off-Drawer Same-Column L3 Sourced Writes with Intervention",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache with intervention"
+	},
+	{
+		"EventCode": "154",
+		"EventName": "L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES",
+		"BriefDescription": "L1D Off-Drawer Same-Column L3 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache without intervention"
+	},
+	{
+		"EventCode": "155",
+		"EventName": "L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES",
+		"BriefDescription": "L1D Off-Drawer Far-Column L3 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-4 cache"
+	},
+	{
+		"EventCode": "156",
+		"EventName": "L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV",
+		"BriefDescription": "L1D Off-Drawer Far-Column L3 Sourced Writes with Intervention",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache with intervention"
+	},
+	{
+		"EventCode": "157",
+		"EventName": "L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES",
+		"BriefDescription": "L1D Off-Drawer Far-Column L3 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache without intervention"
+	},
+	{
+		"EventCode": "158",
+		"EventName": "L1D_ONNODE_MEM_SOURCED_WRITES",
+		"BriefDescription": "L1D On-Node Memory Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Node memory"
+	},
+	{
+		"EventCode": "159",
+		"EventName": "L1D_ONDRAWER_MEM_SOURCED_WRITES",
+		"BriefDescription": "L1D On-Drawer Memory Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer memory"
+	},
+	{
+		"EventCode": "160",
+		"EventName": "L1D_OFFDRAWER_MEM_SOURCED_WRITES",
+		"BriefDescription": "L1D Off-Drawer Memory Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer memory"
+	},
+	{
+		"EventCode": "161",
+		"EventName": "L1D_ONCHIP_MEM_SOURCED_WRITES",
+		"BriefDescription": "L1D On-Chip Memory Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip memory"
+	},
+	{
+		"EventCode": "162",
+		"EventName": "L1I_ONCHIP_L3_SOURCED_WRITES",
+		"BriefDescription": "L1I On-Chip L3 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention"
+	},
+	{
+		"EventCode": "163",
+		"EventName": "L1I_ONCHIP_L3_SOURCED_WRITES_IV",
+		"BriefDescription": "L1I On-Chip L3 Sourced Writes with Intervention",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache with intervention"
+	},
+	{
+		"EventCode": "164",
+		"EventName": "L1I_ONNODE_L4_SOURCED_WRITES",
+		"BriefDescription": "L1I On-Chip L4 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Node Level-4 cache"
+	},
+	{
+		"EventCode": "165",
+		"EventName": "L1I_ONNODE_L3_SOURCED_WRITES_IV",
+		"BriefDescription": "L1I On-Node L3 Sourced Writes with Intervention",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Node Level-3 cache with intervention"
+	},
+	{
+		"EventCode": "166",
+		"EventName": "L1I_ONNODE_L3_SOURCED_WRITES",
+		"BriefDescription": "L1I On-Node L3 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Node Level-3 cache without intervention"
+	},
+	{
+		"EventCode": "167",
+		"EventName": "L1I_ONDRAWER_L4_SOURCED_WRITES",
+		"BriefDescription": "L1I On-Drawer L4 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-4 cache"
+	},
+	{
+		"EventCode": "168",
+		"EventName": "L1I_ONDRAWER_L3_SOURCED_WRITES_IV",
+		"BriefDescription": "L1I On-Drawer L3 Sourced Writes with Intervention",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache with intervention"
+	},
+	{
+		"EventCode": "169",
+		"EventName": "L1I_ONDRAWER_L3_SOURCED_WRITES",
+		"BriefDescription": "L1I On-Drawer L3 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache without intervention"
+	},
+	{
+		"EventCode": "170",
+		"EventName": "L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES",
+		"BriefDescription": "L1I Off-Drawer Same-Column L4 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-4 cache"
+	},
+	{
+		"EventCode": "171",
+		"EventName": "L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV",
+		"BriefDescription": "L1I Off-Drawer Same-Column L3 Sourced Writes with Intervention",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache with intervention"
+	},
+	{
+		"EventCode": "172",
+		"EventName": "L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES",
+		"BriefDescription": "L1I Off-Drawer Same-Column L3 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache without intervention"
+	},
+	{
+		"EventCode": "173",
+		"EventName": "L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES",
+		"BriefDescription": "L1I Off-Drawer Far-Column L4 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-4 cache"
+	},
+	{
+		"EventCode": "174",
+		"EventName": "L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV",
+		"BriefDescription": "L1I Off-Drawer Far-Column L3 Sourced Writes with Intervention",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache with intervention"
+	},
+	{
+		"EventCode": "175",
+		"EventName": "L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES",
+		"BriefDescription": "L1I Off-Drawer Far-Column L3 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache without intervention"
+	},
+	{
+		"EventCode": "176",
+		"EventName": "L1I_ONNODE_MEM_SOURCED_WRITES",
+		"BriefDescription": "L1I On-Node Memory Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Node memory"
+	},
+	{
+		"EventCode": "177",
+		"EventName": "L1I_ONDRAWER_MEM_SOURCED_WRITES",
+		"BriefDescription": "L1I On-Drawer Memory Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer memory"
+	},
+	{
+		"EventCode": "178",
+		"EventName": "L1I_OFFDRAWER_MEM_SOURCED_WRITES",
+		"BriefDescription": "L1I Off-Drawer Memory Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer memory"
+	},
+	{
+		"EventCode": "179",
+		"EventName": "L1I_ONCHIP_MEM_SOURCED_WRITES",
+		"BriefDescription": "L1I On-Chip Memory Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Chip memory"
+	},
+	{
+		"EventCode": "218",
+		"EventName": "TX_NC_TABORT",
+		"BriefDescription": "Aborted transactions in non-constrained TX mode",
+		"PublicDescription": "A transaction abort has occurred in a non-constrained transactional-execution mode"
+	},
+	{
+		"EventCode": "219",
+		"EventName": "TX_C_TABORT_NO_SPECIAL",
+		"BriefDescription": "Aborted transactions in constrained TX mode not using special completion logic",
+		"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete"
+	},
+	{
+		"EventCode": "220",
+		"EventName": "TX_C_TABORT_SPECIAL",
+		"BriefDescription": "Aborted transactions in constrained TX mode using special completion logic",
+		"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete"
+	},
+	{
+		"EventCode": "448",
+		"EventName": "MT_DIAG_CYCLES_ONE_THR_ACTIVE",
+		"BriefDescription": "Cycle count with one thread active",
+		"PublicDescription": "Cycle count with one thread active"
+	},
+	{
+		"EventCode": "449",
+		"EventName": "MT_DIAG_CYCLES_TWO_THR_ACTIVE",
+		"BriefDescription": "Cycle count with two threads active",
+		"PublicDescription": "Cycle count with two threads active"
+	},
+]
diff --git a/tools/perf/pmu-events/arch/s390/mapfile.csv b/tools/perf/pmu-events/arch/s390/mapfile.csv
index c57f8e75fa23..3cff9c64bb85 100644
--- a/tools/perf/pmu-events/arch/s390/mapfile.csv
+++ b/tools/perf/pmu-events/arch/s390/mapfile.csv
@@ -2,3 +2,4 @@ Family-model,Version,Filename,EventType
 209[78],1,cf_z10,core
 281[78],1,cf_z196,core
 282[78],1,cf_zec12,core
+296[45],1,cf_z13,core
-- 
2.14.3

[PATCH 8/8] perf vendor events s390: Add JSON files for IBM z14

[Arnaldo Carvalho de Melo]

From: Thomas Richter <tmricht@linux.vnet.ibm.com>

Add CPU measurement counter facility event description files (json
files) for IBM z14.

Signed-off-by: Thomas Richter <tmricht@linux.vnet.ibm.com>
Reviewed-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Link: http://lkml.kernel.org/r/20180326082538.2258-5-tmricht@linux.vnet.ibm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 tools/perf/pmu-events/arch/s390/cf_z14/basic.json  |  50 ++++
 tools/perf/pmu-events/arch/s390/cf_z14/crypto.json |  98 +++++++
 .../perf/pmu-events/arch/s390/cf_z14/extended.json | 320 +++++++++++++++++++++
 tools/perf/pmu-events/arch/s390/mapfile.csv        |   1 +
 4 files changed, 469 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/s390/cf_z14/basic.json
 create mode 100644 tools/perf/pmu-events/arch/s390/cf_z14/crypto.json
 create mode 100644 tools/perf/pmu-events/arch/s390/cf_z14/extended.json

diff --git a/tools/perf/pmu-events/arch/s390/cf_z14/basic.json b/tools/perf/pmu-events/arch/s390/cf_z14/basic.json
new file mode 100644
index 000000000000..8f653c9d899d
--- /dev/null
+++ b/tools/perf/pmu-events/arch/s390/cf_z14/basic.json
@@ -0,0 +1,50 @@
+[
+	{
+		"EventCode": "0",
+		"EventName": "CPU_CYCLES",
+		"BriefDescription": "CPU Cycles",
+		"PublicDescription": "Cycle Count"
+	},
+	{
+		"EventCode": "1",
+		"EventName": "INSTRUCTIONS",
+		"BriefDescription": "Instructions",
+		"PublicDescription": "Instruction Count"
+	},
+	{
+		"EventCode": "2",
+		"EventName": "L1I_DIR_WRITES",
+		"BriefDescription": "L1I Directory Writes",
+		"PublicDescription": "Level-1 I-Cache Directory Write Count"
+	},
+	{
+		"EventCode": "3",
+		"EventName": "L1I_PENALTY_CYCLES",
+		"BriefDescription": "L1I Penalty Cycles",
+		"PublicDescription": "Level-1 I-Cache Penalty Cycle Count"
+	},
+	{
+		"EventCode": "4",
+		"EventName": "L1D_DIR_WRITES",
+		"BriefDescription": "L1D Directory Writes",
+		"PublicDescription": "Level-1 D-Cache Directory Write Count"
+	},
+	{
+		"EventCode": "5",
+		"EventName": "L1D_PENALTY_CYCLES",
+		"BriefDescription": "L1D Penalty Cycles",
+		"PublicDescription": "Level-1 D-Cache Penalty Cycle Count"
+	},
+	{
+		"EventCode": "32",
+		"EventName": "PROBLEM_STATE_CPU_CYCLES",
+		"BriefDescription": "Problem-State CPU Cycles",
+		"PublicDescription": "Problem-State Cycle Count"
+	},
+	{
+		"EventCode": "33",
+		"EventName": "PROBLEM_STATE_INSTRUCTIONS",
+		"BriefDescription": "Problem-State Instructions",
+		"PublicDescription": "Problem-State Instruction Count"
+	},
+]
diff --git a/tools/perf/pmu-events/arch/s390/cf_z14/crypto.json b/tools/perf/pmu-events/arch/s390/cf_z14/crypto.json
new file mode 100644
index 000000000000..7e5b72492141
--- /dev/null
+++ b/tools/perf/pmu-events/arch/s390/cf_z14/crypto.json
@@ -0,0 +1,98 @@
+[
+	{
+		"EventCode": "64",
+		"EventName": "PRNG_FUNCTIONS",
+		"BriefDescription": "PRNG Functions",
+		"PublicDescription": "Total number of the PRNG functions issued by the CPU"
+	},
+	{
+		"EventCode": "65",
+		"EventName": "PRNG_CYCLES",
+		"BriefDescription": "PRNG Cycles",
+		"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing PRNG functions issued by the CPU"
+	},
+	{
+		"EventCode": "66",
+		"EventName": "PRNG_BLOCKED_FUNCTIONS",
+		"BriefDescription": "PRNG Blocked Functions",
+		"PublicDescription": "Total number of the PRNG functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+	},
+	{
+		"EventCode": "67",
+		"EventName": "PRNG_BLOCKED_CYCLES",
+		"BriefDescription": "PRNG Blocked Cycles",
+		"PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+	},
+	{
+		"EventCode": "68",
+		"EventName": "SHA_FUNCTIONS",
+		"BriefDescription": "SHA Functions",
+		"PublicDescription": "Total number of SHA functions issued by the CPU"
+	},
+	{
+		"EventCode": "69",
+		"EventName": "SHA_CYCLES",
+		"BriefDescription": "SHA Cycles",
+		"PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU"
+	},
+	{
+		"EventCode": "70",
+		"EventName": "SHA_BLOCKED_FUNCTIONS",
+		"BriefDescription": "SHA Blocked Functions",
+		"PublicDescription": "Total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU"
+	},
+	{
+		"EventCode": "71",
+		"EventName": "SHA_BLOCKED_CYCLES",
+		"BriefDescription": "SHA Bloced Cycles",
+		"PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU"
+	},
+	{
+		"EventCode": "72",
+		"EventName": "DEA_FUNCTIONS",
+		"BriefDescription": "DEA Functions",
+		"PublicDescription": "Total number of the DEA functions issued by the CPU"
+	},
+	{
+		"EventCode": "73",
+		"EventName": "DEA_CYCLES",
+		"BriefDescription": "DEA Cycles",
+		"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU"
+	},
+	{
+		"EventCode": "74",
+		"EventName": "DEA_BLOCKED_FUNCTIONS",
+		"BriefDescription": "DEA Blocked Functions",
+		"PublicDescription": "Total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+	},
+	{
+		"EventCode": "75",
+		"EventName": "DEA_BLOCKED_CYCLES",
+		"BriefDescription": "DEA Blocked Cycles",
+		"PublicDescription": "Total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+	},
+	{
+		"EventCode": "76",
+		"EventName": "AES_FUNCTIONS",
+		"BriefDescription": "AES Functions",
+		"PublicDescription": "Total number of AES functions issued by the CPU"
+	},
+	{
+		"EventCode": "77",
+		"EventName": "AES_CYCLES",
+		"BriefDescription": "AES Cycles",
+		"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU"
+	},
+	{
+		"EventCode": "78",
+		"EventName": "AES_BLOCKED_FUNCTIONS",
+		"BriefDescription": "AES Blocked Functions",
+		"PublicDescription": "Total number of AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+	},
+	{
+		"EventCode": "79",
+		"EventName": "AES_BLOCKED_CYCLES",
+		"BriefDescription": "AES Blocked Cycles",
+		"PublicDescription": "Total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+	},
+]
diff --git a/tools/perf/pmu-events/arch/s390/cf_z14/extended.json b/tools/perf/pmu-events/arch/s390/cf_z14/extended.json
new file mode 100644
index 000000000000..aa4dfb46b65b
--- /dev/null
+++ b/tools/perf/pmu-events/arch/s390/cf_z14/extended.json
@@ -0,0 +1,320 @@
+[
+	{
+		"EventCode": "128",
+		"EventName": "L1D_RO_EXCL_WRITES",
+		"BriefDescription": "L1D Read-only Exclusive Writes",
+		"PublicDescription": "Counter:128	Name:L1D_RO_EXCL_WRITES A directory write to the Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line"
+	},
+	{
+		"EventCode": "129",
+		"EventName": "DTLB2_WRITES",
+		"BriefDescription": "DTLB2 Writes",
+		"PublicDescription": "A translation has been written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the data cache"
+	},
+	{
+		"EventCode": "130",
+		"EventName": "DTLB2_MISSES",
+		"BriefDescription": "DTLB2 Misses",
+		"PublicDescription": "A TLB2 miss is in progress for a request made by the data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this cycle"
+	},
+	{
+		"EventCode": "131",
+		"EventName": "DTLB2_HPAGE_WRITES",
+		"BriefDescription": "DTLB2 One-Megabyte Page Writes",
+		"PublicDescription": "A translation entry was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page or a Last Host Translation was done"
+	},
+	{
+		"EventCode": "132",
+		"EventName": "DTLB2_GPAGE_WRITES",
+		"BriefDescription": "DTLB2 Two-Gigabyte Page Writes",
+		"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB"
+	},
+	{
+		"EventCode": "133",
+		"EventName": "L1D_L2D_SOURCED_WRITES",
+		"BriefDescription": "L1D L2D Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache"
+	},
+	{
+		"EventCode": "134",
+		"EventName": "ITLB2_WRITES",
+		"BriefDescription": "ITLB2 Writes",
+		"PublicDescription": "A translation entry has been written into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache"
+	},
+	{
+		"EventCode": "135",
+		"EventName": "ITLB2_MISSES",
+		"BriefDescription": "ITLB2 Misses",
+		"PublicDescription": "A TLB2 miss is in progress for a request made by the instruction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cache in a cycle"
+	},
+	{
+		"EventCode": "136",
+		"EventName": "L1I_L2I_SOURCED_WRITES",
+		"BriefDescription": "L1I L2I Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache"
+	},
+	{
+		"EventCode": "137",
+		"EventName": "TLB2_PTE_WRITES",
+		"BriefDescription": "TLB2 PTE Writes",
+		"PublicDescription": "A translation entry was written into the Page Table Entry array in the Level-2 TLB"
+	},
+	{
+		"EventCode": "138",
+		"EventName": "TLB2_CRSTE_WRITES",
+		"BriefDescription": "TLB2 CRSTE Writes",
+		"PublicDescription": "Translation entries were written into the Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB"
+	},
+	{
+		"EventCode": "139",
+		"EventName": "TLB2_ENGINES_BUSY",
+		"BriefDescription": "TLB2 Engines Busy",
+		"PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle"
+	},
+	{
+		"EventCode": "140",
+		"EventName": "TX_C_TEND",
+		"BriefDescription": "Completed TEND instructions in constrained TX mode",
+		"PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode"
+	},
+	{
+		"EventCode": "141",
+		"EventName": "TX_NC_TEND",
+		"BriefDescription": "Completed TEND instructions in non-constrained TX mode",
+		"PublicDescription": "A TEND instruction has completed in a non-constrained transactional-execution mode"
+	},
+	{
+		"EventCode": "143",
+		"EventName": "L1C_TLB2_MISSES",
+		"BriefDescription": "L1C TLB2 Misses",
+		"PublicDescription": "Increments by one for any cycle where a level-1 cache or level-2 TLB miss is in progress"
+	},
+	{
+		"EventCode": "144",
+		"EventName": "L1D_ONCHIP_L3_SOURCED_WRITES",
+		"BriefDescription": "L1D On-Chip L3 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention"
+	},
+	{
+		"EventCode": "145",
+		"EventName": "L1D_ONCHIP_MEMORY_SOURCED_WRITES",
+		"BriefDescription": "L1D On-Chip Memory Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip memory"
+	},
+	{
+		"EventCode": "146",
+		"EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_IV",
+		"BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache with intervention"
+	},
+	{
+		"EventCode": "147",
+		"EventName": "L1D_ONCLUSTER_L3_SOURCED_WRITES",
+		"BriefDescription": "L1D On-Cluster L3 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Cluster Level-3 cache withountervention"
+	},
+	{
+		"EventCode": "148",
+		"EventName": "L1D_ONCLUSTER_MEMORY_SOURCED_WRITES",
+		"BriefDescription": "L1D On-Cluster Memory Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Cluster memory"
+	},
+	{
+		"EventCode": "149",
+		"EventName": "L1D_ONCLUSTER_L3_SOURCED_WRITES_IV",
+		"BriefDescription": "L1D On-Cluster L3 Sourced Writes with Intervention",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Cluster Level-3 cache with intervention"
+	},
+	{
+		"EventCode": "150",
+		"EventName": "L1D_OFFCLUSTER_L3_SOURCED_WRITES",
+		"BriefDescription": "L1D Off-Cluster L3 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache without intervention"
+	},
+	{
+		"EventCode": "151",
+		"EventName": "L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES",
+		"BriefDescription": "L1D Off-Cluster Memory Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Cluster memory"
+	},
+	{
+		"EventCode": "152",
+		"EventName": "L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV",
+		"BriefDescription": "L1D Off-Cluster L3 Sourced Writes with Intervention",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache with intervention"
+	},
+	{
+		"EventCode": "153",
+		"EventName": "L1D_OFFDRAWER_L3_SOURCED_WRITES",
+		"BriefDescription": "L1D Off-Drawer L3 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache without intervention"
+	},
+	{
+		"EventCode": "154",
+		"EventName": "L1D_OFFDRAWER_MEMORY_SOURCED_WRITES",
+		"BriefDescription": "L1D Off-Drawer Memory Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer memory"
+	},
+	{
+		"EventCode": "155",
+		"EventName": "L1D_OFFDRAWER_L3_SOURCED_WRITES_IV",
+		"BriefDescription": "L1D Off-Drawer L3 Sourced Writes with Intervention",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache with intervention"
+	},
+	{
+		"EventCode": "156",
+		"EventName": "L1D_ONDRAWER_L4_SOURCED_WRITES",
+		"BriefDescription": "L1D On-Drawer L4 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer Level-4 cache"
+	},
+	{
+		"EventCode": "157",
+		"EventName": "L1D_OFFDRAWER_L4_SOURCED_WRITES",
+		"BriefDescription": "L1D Off-Drawer L4 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer Level-4 cache"
+	},
+	{
+		"EventCode": "158",
+		"EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_RO",
+		"BriefDescription": "L1D On-Chip L3 Sourced Writes read-only",
+		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip L3 but a read-only invalidate was done to remove other copies of the cache line"
+	},
+	{
+		"EventCode": "162",
+		"EventName": "L1I_ONCHIP_L3_SOURCED_WRITES",
+		"BriefDescription": "L1I On-Chip L3 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from an On-Chip Level-3 cache without intervention"
+	},
+	{
+		"EventCode": "163",
+		"EventName": "L1I_ONCHIP_MEMORY_SOURCED_WRITES",
+		"BriefDescription": "L1I On-Chip Memory Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from On-Chip memory"
+	},
+	{
+		"EventCode": "164",
+		"EventName": "L1I_ONCHIP_L3_SOURCED_WRITES_IV",
+		"BriefDescription": "L1I On-Chip L3 Sourced Writes with Intervention",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from an On-Chip Level-3 cache with intervention"
+	},
+	{
+		"EventCode": "165",
+		"EventName": "L1I_ONCLUSTER_L3_SOURCED_WRITES",
+		"BriefDescription": "L1I On-Cluster L3 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Cluster Level-3 cache without intervention"
+	},
+	{
+		"EventCode": "166",
+		"EventName": "L1I_ONCLUSTER_MEMORY_SOURCED_WRITES",
+		"BriefDescription": "L1I On-Cluster Memory Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Cluster memory"
+	},
+	{
+		"EventCode": "167",
+		"EventName": "L1I_ONCLUSTER_L3_SOURCED_WRITES_IV",
+		"BriefDescription": "L1I On-Cluster L3 Sourced Writes with Intervention",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Cluster Level-3 cache with intervention"
+	},
+	{
+		"EventCode": "168",
+		"EventName": "L1I_OFFCLUSTER_L3_SOURCED_WRITES",
+		"BriefDescription": "L1I Off-Cluster L3 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache without intervention"
+	},
+	{
+		"EventCode": "169",
+		"EventName": "L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES",
+		"BriefDescription": "L1I Off-Cluster Memory Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Cluster memory"
+	},
+	{
+		"EventCode": "170",
+		"EventName": "L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV",
+		"BriefDescription": "L1I Off-Cluster L3 Sourced Writes with Intervention",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache with intervention"
+	},
+	{
+		"EventCode": "171",
+		"EventName": "L1I_OFFDRAWER_L3_SOURCED_WRITES",
+		"BriefDescription": "L1I Off-Drawer L3 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache without intervention"
+	},
+	{
+		"EventCode": "172",
+		"EventName": "L1I_OFFDRAWER_MEMORY_SOURCED_WRITES",
+		"BriefDescription": "L1I Off-Drawer Memory Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer memory"
+	},
+	{
+		"EventCode": "173",
+		"EventName": "L1I_OFFDRAWER_L3_SOURCED_WRITES_IV",
+		"BriefDescription": "L1I Off-Drawer L3 Sourced Writes with Intervention",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache with intervention"
+	},
+	{
+		"EventCode": "174",
+		"EventName": "L1I_ONDRAWER_L4_SOURCED_WRITES",
+		"BriefDescription": "L1I On-Drawer L4 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer Level-4 cache"
+	},
+	{
+		"EventCode": "175",
+		"EventName": "L1I_OFFDRAWER_L4_SOURCED_WRITES",
+		"BriefDescription": "L1I Off-Drawer L4 Sourced Writes",
+		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer Level-4 cache"
+	},
+	{
+		"EventCode": "224",
+		"EventName": "BCD_DFP_EXECUTION_SLOTS",
+		"BriefDescription": "BCD DFP Execution Slots",
+		"PublicDescription": "Count of floating point execution slots used for finished Binary Coded Decimal to Decimal Floating Point conversions. Instructions: CDZT, CXZT, CZDT, CZXT"
+	},
+	{
+		"EventCode": "225",
+		"EventName": "VX_BCD_EXECUTION_SLOTS",
+		"BriefDescription": "VX BCD Execution Slots",
+		"PublicDescription": "Count of floating point execution slots used for finished vector arithmetic Binary Coded Decimal instructions. Instructions: VAP, VSP, VMPVMSP, VDP, VSDP, VRP, VLIP, VSRP, VPSOPVCP, VTP, VPKZ, VUPKZ, VCVB, VCVBG, VCVDVCVDG"
+	},
+	{
+		"EventCode": "226",
+		"EventName": "DECIMAL_INSTRUCTIONS",
+		"BriefDescription": "Decimal Instructions",
+		"PublicDescription": "Decimal instructions dispatched. Instructions: CVB, CVD, AP, CP, DP, ED, EDMK, MP, SRP, SP, ZAP"
+	},
+	{
+		"EventCode": "232",
+		"EventName": "LAST_HOST_TRANSLATIONS",
+		"BriefDescription": "Last host translation done",
+		"PublicDescription": "Last Host Translation done"
+	},
+	{
+		"EventCode": "243",
+		"EventName": "TX_NC_TABORT",
+		"BriefDescription": "Aborted transactions in non-constrained TX mode",
+		"PublicDescription": "A transaction abort has occurred in a non-constrained transactional-execution mode"
+	},
+	{
+		"EventCode": "244",
+		"EventName": "TX_C_TABORT_NO_SPECIAL",
+		"BriefDescription": "Aborted transactions in constrained TX mode not using special completion logic",
+		"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete"
+	},
+	{
+		"EventCode": "245",
+		"EventName": "TX_C_TABORT_SPECIAL",
+		"BriefDescription": "Aborted transactions in constrained TX mode using special completion logic",
+		"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete"
+	},
+	{
+		"EventCode": "448",
+		"EventName": "MT_DIAG_CYCLES_ONE_THR_ACTIVE",
+		"BriefDescription": "Cycle count with one thread active",
+		"PublicDescription": "Cycle count with one thread active"
+	},
+	{
+		"EventCode": "449",
+		"EventName": "MT_DIAG_CYCLES_TWO_THR_ACTIVE",
+		"BriefDescription": "Cycle count with two threads active",
+		"PublicDescription": "Cycle count with two threads active"
+	},
+]
diff --git a/tools/perf/pmu-events/arch/s390/mapfile.csv b/tools/perf/pmu-events/arch/s390/mapfile.csv
index 3cff9c64bb85..ca7682748a4b 100644
--- a/tools/perf/pmu-events/arch/s390/mapfile.csv
+++ b/tools/perf/pmu-events/arch/s390/mapfile.csv
@@ -3,3 +3,4 @@ Family-model,Version,Filename,EventType
 281[78],1,cf_z196,core
 282[78],1,cf_zec12,core
 296[45],1,cf_z13,core
+3906,3,cf_z14,core
-- 
2.14.3

Re: [GIT PULL 0/8] perf/core improvements and fixes

[Ingo Molnar]

* Arnaldo Carvalho de Melo <acme@kernel.org> wrote:

> Hi Ingo,
> 
> 	Please consider pulling,
> 
> - Arnaldo
> 
> Test results at the end of this message, as usual.
> 
> The following changes since commit 631fe154edb0a37308d0116a0f9b7bba9dca6218:
> 
>   perf/x86: Update rdpmc_always_available static key to the modern API (2018-03-27 07:53:00 +0200)
> 
> are available in the Git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git tags/perf-core-for-mingo-4.17-20180328
> 
> for you to fetch changes up to 109d59b900e78834c66657dd4748fcedb9a1fe8d:
> 
>   perf vendor events s390: Add JSON files for IBM z14 (2018-03-27 13:13:39 -0300)
> 
> ----------------------------------------------------------------
> perf/core improvements and fixes:
> 
> - Be consistent when checking if a perf_mmap instance had
>   its ring buffer unmmaped, fixing segfaults noticed in
>   'perf trace' (Kan Liang, Arnaldo Carvalho de Melo)
> 
> - Avoid adding the same option multiple times to the 'diff'
>   command in check-headers.sh (Jiri Olsa)
> 
> - Add vendor event files (JSON format) to various IBM
>   s390 models (z10EC, z10BC, z196, zEC12, zBC12, z13
>   and z14) (Thomas Richter)
> 
> Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> 
> ----------------------------------------------------------------
> Arnaldo Carvalho de Melo (1):
>       perf mmap: Be consistent when checking for an unmaped ring buffer
> 
> Jiri Olsa (1):
>       perf build: Fix check-headers.sh opts assignment
> 
> Kan Liang (1):
>       perf mmap: Fix accessing unmapped mmap in perf_mmap__read_done()
> 
> Thomas Richter (5):
>       perf vendor events s390: Add JSON files for IBM z10EC z10BC
>       perf vendor events s390: Add JSON files for IBM z196
>       perf vendor events s390: Add JSON files for IBM zEC12 zBC12
>       perf vendor events s390: Add JSON files for IBM z13
>       perf vendor events s390: Add JSON files for IBM z14
> 
>  tools/perf/check-headers.sh                        |   1 +
>  tools/perf/pmu-events/arch/s390/cf_z10/basic.json  |  74 +++++
>  tools/perf/pmu-events/arch/s390/cf_z10/crypto.json |  98 ++++++
>  .../perf/pmu-events/arch/s390/cf_z10/extended.json | 110 +++++++
>  tools/perf/pmu-events/arch/s390/cf_z13/basic.json  |  74 +++++
>  tools/perf/pmu-events/arch/s390/cf_z13/crypto.json |  98 ++++++
>  .../perf/pmu-events/arch/s390/cf_z13/extended.json | 338 +++++++++++++++++++++
>  tools/perf/pmu-events/arch/s390/cf_z14/basic.json  |  50 +++
>  tools/perf/pmu-events/arch/s390/cf_z14/crypto.json |  98 ++++++
>  .../perf/pmu-events/arch/s390/cf_z14/extended.json | 320 +++++++++++++++++++
>  tools/perf/pmu-events/arch/s390/cf_z196/basic.json |  74 +++++
>  .../perf/pmu-events/arch/s390/cf_z196/crypto.json  |  98 ++++++
>  .../pmu-events/arch/s390/cf_z196/extended.json     | 146 +++++++++
>  .../perf/pmu-events/arch/s390/cf_zec12/basic.json  |  74 +++++
>  .../perf/pmu-events/arch/s390/cf_zec12/crypto.json |  98 ++++++
>  .../pmu-events/arch/s390/cf_zec12/extended.json    | 212 +++++++++++++
>  tools/perf/pmu-events/arch/s390/mapfile.csv        |   6 +
>  tools/perf/util/mmap.c                             |  19 +-
>  18 files changed, 1987 insertions(+), 1 deletion(-)
>  create mode 100644 tools/perf/pmu-events/arch/s390/cf_z10/basic.json
>  create mode 100644 tools/perf/pmu-events/arch/s390/cf_z10/crypto.json
>  create mode 100644 tools/perf/pmu-events/arch/s390/cf_z10/extended.json
>  create mode 100644 tools/perf/pmu-events/arch/s390/cf_z13/basic.json
>  create mode 100644 tools/perf/pmu-events/arch/s390/cf_z13/crypto.json
>  create mode 100644 tools/perf/pmu-events/arch/s390/cf_z13/extended.json
>  create mode 100644 tools/perf/pmu-events/arch/s390/cf_z14/basic.json
>  create mode 100644 tools/perf/pmu-events/arch/s390/cf_z14/crypto.json
>  create mode 100644 tools/perf/pmu-events/arch/s390/cf_z14/extended.json
>  create mode 100644 tools/perf/pmu-events/arch/s390/cf_z196/basic.json
>  create mode 100644 tools/perf/pmu-events/arch/s390/cf_z196/crypto.json
>  create mode 100644 tools/perf/pmu-events/arch/s390/cf_z196/extended.json
>  create mode 100644 tools/perf/pmu-events/arch/s390/cf_zec12/basic.json
>  create mode 100644 tools/perf/pmu-events/arch/s390/cf_zec12/crypto.json
>  create mode 100644 tools/perf/pmu-events/arch/s390/cf_zec12/extended.json
>  create mode 100644 tools/perf/pmu-events/arch/s390/mapfile.csv

Pulled, thanks a lot Arnaldo!

	Ingo