Re: [PATCH 0/2] perf: riscv: Preliminary Perf Event Support on RISC-V

Palmer Dabbelt
2018-04-03T03:15:47Z

On Mon, 02 Apr 2018 05:31:22 PDT (-0700), alankao@andestech.com wrote:
> This implements the baseline PMU for RISC-V platforms.
>
> To ease future PMU portings, a guide is also written, containing
> perf concepts, arch porting practices and some hints.
>
> Changes in v2:
> - Fix the bug reported by Alex, which was caused by not sufficient
> initialization. Check https://lkml.org/lkml/2018/3/31/251 for the
> discussion.
>
> Alan Kao (2):
> perf: riscv: preliminary RISC-V support
> perf: riscv: Add Document for Future Porting Guide
>
> Documentation/riscv/pmu.txt | 249 +++++++++++++++++++
> arch/riscv/Kconfig | 12 +
> arch/riscv/include/asm/perf_event.h | 76 +++++-
> arch/riscv/kernel/Makefile | 1 +
> arch/riscv/kernel/perf_event.c | 468 ++++++++++++++++++++++++++++++++++++
> 5 files changed, 802 insertions(+), 4 deletions(-)
> create mode 100644 Documentation/riscv/pmu.txt
> create mode 100644 arch/riscv/kernel/perf_event.c

I'm having some trouble pulling this into my tree. I think you might have
another patch floating around somewhere, as I don't have any
arch/riscv/include/asm/perf_event.h right now.

Do you mind rebasing this on top of linux-4.16 so I can look properly?

Thanks!