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Mon, 30 Apr 2018 01:58:53 -0400 Received: from mail.bootlin.com ([62.4.15.54]:50942 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751589AbeD3F6w (ORCPT ); Mon, 30 Apr 2018 01:58:52 -0400 X-Remote-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.bootlin.com X-Remote-Spam-Level: X-Remote-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_RED shortcircuit=ham autolearn=disabled version=3.4.0 Date: Mon, 30 Apr 2018 07:58:47 +0200 From: Boris Brezillon To: Marcin Ziemianowicz Cc: Boris Brezillon , Nicolas Ferre , Alexandre Belloni , Greg Kroah-Hartman , stable@vger.kernel.org, Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH V4] clk: at91: PLL recalc_rate() now using cached MUL and DIV values Message-ID: <20180430075847.29706679@bbrezillon> In-Reply-To: <20180429190111.14247-1-marcin@ziemianowicz.com> References: <20180429190111.14247-1-marcin@ziemianowicz.com> X-Mailer: Claws Mail 3.15.0-dirty (GTK+ 2.24.31; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: stable-owner@vger.kernel.org X-Mailing-List: stable@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-Mailing-List: linux-kernel@vger.kernel.org List-ID: On Sun, 29 Apr 2018 15:01:11 -0400 Marcin Ziemianowicz wrote: > When a USB device is connected to the USB host port on the SAM9N12 then > you get "-62" error which seems to indicate USB replies from the device > are timing out. Based on a logic sniffer, I saw the USB bus was running > at half speed. > > The PLL code uses cached MUL and DIV values which get set in set_rate() > and applied in prepare(), but the recalc_rate() function instead > queries the hardware instead of using these cached values. Therefore, > if recalc_rate() is called between a set_rate() and prepare(), the > wrong frequency is calculated and later the USB clock divider for the > SAM9N12 SOC will be configured for an incorrect clock. > > In my case, the PLL hardware was set to 96 Mhz before the OHCI > driver loads, and therefore the usb clock divider was being set > to /2 even though the OHCI driver set the PLL to 48 Mhz. > > As an alternative explanation, I noticed this was fixed in the past by > 87e2ed338f1b ("clk: at91: fix recalc_rate implementation of PLL > driver") but the bug was later re-introduced by 1bdf02326b71 ("clk: > at91: make use of syscon/regmap internally"). > > Fixes: 1bdf02326b71 ("clk: at91: make use of syscon/regmap internally) > Cc: > Signed-off-by: Marcin Ziemianowicz Acked-by: Boris Brezillon > --- > Thank you for bearing with me about this Boris. > > Changes since V3: > Fix for double returns found by kbluild test robot > > Comments by Boris Brezillon about email formatting issues > Changes since V2: > Removed all logging/debug messages I added > > Comment by Boris Brezillon about my fix being wrong addressed > Changes since V1: > Added patch set cover letter > Shortened lines which were over >80 characters long > > Comment by Greg Kroah-Hartman about "from" field in email addressed > > Comment by Alan Stern about redundant debug lines addressed > > drivers/clk/at91/clk-pll.c | 13 +------------ > 1 file changed, 1 insertion(+), 12 deletions(-) > > diff --git a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c > index 7d3223fc..72b6091e 100644 > --- a/drivers/clk/at91/clk-pll.c > +++ b/drivers/clk/at91/clk-pll.c > @@ -132,19 +132,8 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, > unsigned long parent_rate) > { > struct clk_pll *pll = to_clk_pll(hw); > - unsigned int pllr; > - u16 mul; > - u8 div; > - > - regmap_read(pll->regmap, PLL_REG(pll->id), &pllr); > - > - div = PLL_DIV(pllr); > - mul = PLL_MUL(pllr, pll->layout); > - > - if (!div || !mul) > - return 0; > > - return (parent_rate / div) * (mul + 1); > + return (parent_rate / pll->div) * (pll->mul + 1); > } > > static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate,