Re: [PATCH v1 1/4] clk: tegra20: Add DEV1/DEV2 OSC dividers

Peter De Schrijver
2018-04-30T07:49:02Z

On Fri, Apr 27, 2018 at 02:58:15AM +0300, Dmitry Osipenko wrote:
> CDEV1/CDEV2 clocks could have corresponding oscillator clock divider as
> a parent. Add these dividers in order to be able to provide that parent
> option.
>
> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> ---
> drivers/clk/tegra/clk-tegra20.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
> index 0ee56dd04cec..16cf4108f2ff 100644
> --- a/drivers/clk/tegra/clk-tegra20.c
> +++ b/drivers/clk/tegra/clk-tegra20.c
> @@ -26,6 +26,8 @@
> #include "clk.h"
> #include "clk-id.h"
>
> +#define MISC_CLK_ENB 0x48
> +
> #define OSC_CTRL 0x50
> #define OSC_CTRL_OSC_FREQ_MASK (3<<30)
> #define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
> @@ -831,6 +833,16 @@ static void __init tegra20_periph_clk_init(void)
> periph_clk_enb_refcnt);
> clks[TEGRA20_CLK_PEX] = clk;
>
> + /* cdev1 OSC divider */
> + clk_register_divider(NULL, "cdev1_osc_div", "clk_m",
> + 0, clk_base + MISC_CLK_ENB, 20, 2,
> + CLK_DIVIDER_POWER_OF_TWO, NULL);
> +

I don't know if this divider can be changed glitchlessly so to be safe,
I would mark this readonly, so add the CLK_DIVIDER_READ_ONLY flag.

> + /* cdev2 OSC divider */
> + clk_register_divider(NULL, "cdev2_osc_div", "clk_m",
> + 0, clk_base + MISC_CLK_ENB, 22, 2,
> + CLK_DIVIDER_POWER_OF_TWO, NULL);
> +
> /* cdev1 */
> clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, 0, 26000000);
> clk = tegra_clk_register_periph_gate("cdev1", "cdev1_fixed", 0,
> --
> 2.17.0
>

Peter.