From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754154AbeD3Rbv (ORCPT ); Mon, 30 Apr 2018 13:31:51 -0400 Received: from muru.com ([72.249.23.125]:39324 "EHLO muru.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752732AbeD3Rbt (ORCPT ); Mon, 30 Apr 2018 13:31:49 -0400 Date: Mon, 30 Apr 2018 10:31:46 -0700 From: Tony Lindgren To: Christina Quast Cc: linux-omap@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, narmstrong@baylibre.com, Oleg Kokorin Subject: Re: [PATCH 1/2] ARM: dts: am335x: Replace numeric pinmux address with macro defines Message-ID: <20180430173146.GG5671@atomide.com> References: <20180430112006.20861-1-cquast@baylibre.com> <20180430112006.20861-2-cquast@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20180430112006.20861-2-cquast@baylibre.com> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, * Christina Quast [180430 11:23]: > The values are extraced from the "AM335x SitaraTM Processors Technical > Reference Manual", Section 9.3.1 CONTROL_MODULE Registers, based on the > file autogenerated by TI PinMux. This certainly makes things easier to mux :) Have you verified that the registers are the same across all am335x models and different revisions? It used to be that different SoC revisions could have different amount of registers and also different options in some cases. > +#define AM335X_CONTROL_REVISION 0x0 > +#define AM335X_CONTROL_HWINFO 0x4 > +#define AM335X_CONTROL_SYSCONFIG 0x10 > +#define AM335X_CONTROL_STATUS 0x40 You should only list the padconf mux registers here, no need to list any of the controller registers. Regards, Tony