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Thu, 3 May 2018 03:03:52 -0400 Received: from mail.bootlin.com ([62.4.15.54]:43317 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751951AbeECHDv (ORCPT ); Thu, 3 May 2018 03:03:51 -0400 X-Remote-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.bootlin.com X-Remote-Spam-Level: X-Remote-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT shortcircuit=ham autolearn=disabled version=3.4.0 Date: Thu, 3 May 2018 09:03:48 +0200 From: Boris Brezillon To: Chris Packham Cc: "miquel.raynal@bootlin.com" , Richard Weinberger , "linux-kernel@vger.kernel.org" , "stable@vger.kernel.org" , Marek Vasut , "linux-mtd@lists.infradead.org" , Brian Norris , David Woodhouse Subject: Re: [PATCH] mtd: rawnand: marvell: pass ms delay to wait_op Message-ID: <20180503090348.0c10b00f@bbrezillon> In-Reply-To: References: <20180503022128.10702-1-chris.packham@alliedtelesis.co.nz> X-Mailer: Claws Mail 3.15.0-dirty (GTK+ 2.24.31; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: stable-owner@vger.kernel.org X-Mailing-List: stable@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-Mailing-List: linux-kernel@vger.kernel.org List-ID: Hi Chris, On Thu, 3 May 2018 05:28:32 +0000 Chris Packham wrote: > On 03/05/18 14:21, Chris Packham wrote: > > marvell_nfc_wait_op() expects the delay to be expressed in milliseconds > > but nand_sdr_timings uses picoseconds. Use PSEC_TO_MSEC when passing > > tPROG_max to marvell_nfc_wait_op(). > > > > Fixes: 02f26ecf8c772 ("mtd: nand: add reworked Marvell NAND controller driver") > > Cc: stable@vger.kernel.org > > Signed-off-by: Chris Packham > > --- > > drivers/mtd/nand/raw/marvell_nand.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/mtd/nand/raw/marvell_nand.c b/drivers/mtd/nand/raw/marvell_nand.c > > index 1d779a35ac8e..e4b964fd40d8 100644 > > --- a/drivers/mtd/nand/raw/marvell_nand.c > > +++ b/drivers/mtd/nand/raw/marvell_nand.c > > @@ -1074,7 +1074,7 @@ static int marvell_nfc_hw_ecc_hmg_do_write_page(struct nand_chip *chip, > > return ret; > > > > ret = marvell_nfc_wait_op(chip, > > - chip->data_interface.timings.sdr.tPROG_max); > > + PSEC_TO_MSEC(chip->data_interface.timings.sdr.tPROG_max)); > > return ret; > > } > > > > @@ -1494,7 +1494,7 @@ static int marvell_nfc_hw_ecc_bch_write_page(struct mtd_info *mtd, > > } > > > > ret = marvell_nfc_wait_op(chip, > > - chip->data_interface.timings.sdr.tPROG_max); > > + PSEC_TO_MSEC(chip->data_interface.timings.sdr.tPROG_max)); > > > > marvell_nfc_disable_hw_ecc(chip); > > > > Actually I'm not so sure about this patch. While passing the pico-second > value for tPROG_max is clearly wrong and leads to seemingly indefinite > hangs on some systems. Converting the times to micro-seconds leaves us > with delays that are far too short. What makes you think they are far too short? > > The old pxa3xx driver had hard coded 200ms delays. These delays now work > out to 1ms which seems every bit as wrong as 600000000ms. The old driver was indifferently waiting a huge amount of time no matter how long the chip is supposed to stay busy for a specific operation. Here we're using the value exposed by the chip itself, and it's not a typical value, it's a max value, which means you should never reach that in real life, and if you do that means your chip is stuck for some reasons. Now, if you want to take extra safety margin, you can multiply the value by 2 and that should be enough, but 200ms is way too long. Regards, Boris