From: Dmitry Osipenko <digetx@gmail.com>
To: "Rafael J. Wysocki" <rjw@rjwysocki.net>,
Viresh Kumar <viresh.kumar@linaro.org>,
Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v1 1/2] cpufreq: tegra20: Constify rate value of the intermediate clk
Date: Wed, 23 May 2018 19:00:19 +0300 [thread overview]
Message-ID: <20180523160020.15291-1-digetx@gmail.com> (raw)
PLL_P is known to be always running at 216MHz, hence there is no need to
query its rate.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
drivers/cpufreq/tegra20-cpufreq.c | 12 +++++-------
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/cpufreq/tegra20-cpufreq.c b/drivers/cpufreq/tegra20-cpufreq.c
index 05f57dcd5215..3ad6bded6efc 100644
--- a/drivers/cpufreq/tegra20-cpufreq.c
+++ b/drivers/cpufreq/tegra20-cpufreq.c
@@ -24,6 +24,8 @@
#include <linux/platform_device.h>
#include <linux/types.h>
+#define PLL_P_FREQ 216000
+
static struct cpufreq_frequency_table freq_table[] = {
{ .frequency = 216000 },
{ .frequency = 312000 },
@@ -48,18 +50,15 @@ struct tegra20_cpufreq {
static unsigned int tegra_get_intermediate(struct cpufreq_policy *policy,
unsigned int index)
{
- struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data();
- unsigned int ifreq = clk_get_rate(cpufreq->pll_p_clk) / 1000;
-
/*
* Don't switch to intermediate freq if:
* - we are already at it, i.e. policy->cur == ifreq
* - index corresponds to ifreq
*/
- if (freq_table[index].frequency == ifreq || policy->cur == ifreq)
+ if (index == 0 || policy->cur == PLL_P_FREQ)
return 0;
- return ifreq;
+ return PLL_P_FREQ;
}
static int tegra_target_intermediate(struct cpufreq_policy *policy,
@@ -93,14 +92,13 @@ static int tegra_target(struct cpufreq_policy *policy, unsigned int index)
{
struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data();
unsigned long rate = freq_table[index].frequency;
- unsigned int ifreq = clk_get_rate(cpufreq->pll_p_clk) / 1000;
int ret;
/*
* target freq == pll_p, don't need to take extra reference to pll_x_clk
* as it isn't used anymore.
*/
- if (rate == ifreq)
+ if (index == 0)
return clk_set_parent(cpufreq->cpu_clk, cpufreq->pll_p_clk);
ret = clk_set_rate(cpufreq->pll_x_clk, rate * 1000);
--
2.17.0
next reply other threads:[~2018-05-23 16:01 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-23 16:00 Dmitry Osipenko [this message]
2018-05-23 16:00 ` [PATCH v1 2/2] cpufreq: tegra20: Use PLL_C as intermediate clock source Dmitry Osipenko
2018-05-24 4:30 ` Viresh Kumar
2018-05-24 5:37 ` Dmitry Osipenko
2018-05-24 8:01 ` Rafael J. Wysocki
2018-05-24 12:28 ` Dmitry Osipenko
2018-05-25 8:14 ` Rafael J. Wysocki
2018-05-25 8:36 ` Rafael J. Wysocki
2018-05-25 8:41 ` Dmitry Osipenko
2018-05-24 10:04 ` Peter De Schrijver
2018-05-24 12:49 ` Dmitry Osipenko
2018-05-25 6:32 ` Peter De Schrijver
2018-05-25 8:28 ` Dmitry Osipenko
2018-05-24 4:27 ` [PATCH v1 1/2] cpufreq: tegra20: Constify rate value of the intermediate clk Viresh Kumar
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