From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp.codeaurora.org by pdx-caf-mail.web.codeaurora.org (Dovecot) with LMTP id VyhiLPVMGVukZQAAmS7hNA ; Thu, 07 Jun 2018 15:19:20 +0000 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 9EF116089E; Thu, 7 Jun 2018 15:19:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI autolearn=ham autolearn_force=no version=3.4.0 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by smtp.codeaurora.org (Postfix) with ESMTP id 144A1606DD; Thu, 7 Jun 2018 15:19:19 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 144A1606DD Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=bootlin.com Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S936071AbeFGPTR convert rfc822-to-8bit (ORCPT + 25 others); Thu, 7 Jun 2018 11:19:17 -0400 Received: from mail.bootlin.com ([62.4.15.54]:49400 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934876AbeFGPTN (ORCPT ); Thu, 7 Jun 2018 11:19:13 -0400 Received: by mail.bootlin.com (Postfix, from userid 110) id B76F9203EC; Thu, 7 Jun 2018 17:19:11 +0200 (CEST) Received: from xps13 (AAubervilliers-681-1-128-7.w90-88.abo.wanadoo.fr [90.88.9.7]) by mail.bootlin.com (Postfix) with ESMTPSA id 6A439203EC; Thu, 7 Jun 2018 17:19:11 +0200 (CEST) Date: Thu, 7 Jun 2018 17:19:11 +0200 From: Miquel Raynal To: Martin Kaiser Cc: Boris Brezillon , David Woodhouse , Sascha Hauer , Fabio Estevam , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: Re: [PATCH] mtd: rawnand: mxc: set spare area size register explicitly Message-ID: <20180607171911.7a7ee649@xps13> In-Reply-To: <1528025495-14443-1-git-send-email-martin@kaiser.cx> References: <1528025495-14443-1-git-send-email-martin@kaiser.cx> Organization: Bootlin X-Mailer: Claws Mail 3.15.0-dirty (GTK+ 2.24.31; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Martin, On Sun, 3 Jun 2018 13:31:35 +0200, Martin Kaiser wrote: > The v21 version of the NAND flash controller contains a Spare Area Size > Register (SPAS) at offset 0x10. Its setting defaults to the maximum > spare area size of 218 bytes. The size that is set in this register is > used by the controller when it calculates the ECC bytes internally in > hardware. > > Usually, this register is updated from settings in the IIM fuses when > the system is booting from nand flash. For other boot media, however, s/nand/NAND > the SPAS register remains at the default setting, which may not work for > the particular flash chip on the board. The same goes for flash chips > whose configuration cannot be set in the IIM fuses (e.g. chips with 2k > sector size and 128 bytes spare area size can't be configured in the IIM > fuses on imx25 systems). > > Set the SPAS register explicitly during the preset operation. Derive the > register value from mtd->oobsize that was detected during probe by > decoding the flash chip's ID bytes. > > While at it, rename the define for the spare area register's offset to > NFC_V21_RSLTSPARE_AREA. The register at offset 0x10 on v1 controllers is > different from the register on v21 controllers. > > Signed-off-by: Martin Kaiser > Cc: stable@vger.kernel.org > --- > drivers/mtd/nand/raw/mxc_nand.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/mtd/nand/raw/mxc_nand.c b/drivers/mtd/nand/raw/mxc_nand.c > index 45786e7..c2f8572 100644 > --- a/drivers/mtd/nand/raw/mxc_nand.c > +++ b/drivers/mtd/nand/raw/mxc_nand.c > @@ -48,7 +48,7 @@ > #define NFC_V1_V2_CONFIG (host->regs + 0x0a) > #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c) > #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e) > -#define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10) > +#define NFC_V21_RSLTSPARE_AREA (host->regs + 0x10) > #define NFC_V1_V2_WRPROT (host->regs + 0x12) > #define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14) > #define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16) > @@ -1274,6 +1274,9 @@ static void preset_v2(struct mtd_info *mtd) > writew(config1, NFC_V1_V2_CONFIG1); > /* preset operation */ > > + /* spare area size in 16bit words */ I thought I understood the problem with your commit message but then I don't get this comment. What's the link between 16-bit buses? Is this preset valid for both 8 and 16-bit bus width? > + writew(mtd->oobsize >> 1, NFC_V21_RSLTSPARE_AREA); > + If this is for dividing per two oobsize value, I would really prefer a '/ 2' and let the compiler optimize things. Unless the spec is explicit about some shifting of course. > /* Unlock the internal RAM Buffer */ > writew(0x2, NFC_V1_V2_CONFIG); > Thanks for fixing this. Regards, Miquèl