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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id 15-v6sm21186954pfq.81.2018.06.22.10.07.59 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 22 Jun 2018 10:08:00 -0700 (PDT) Date: Fri, 22 Jun 2018 10:07:58 -0700 From: Bjorn Andersson To: Rishabh Bhatnagar Cc: linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm@lists.infradead.org, tsoni@codeaurora.org, ckadabi@codeaurora.org, evgreen@chromium.org, robh@kernel.org, andy.shevchenko@gmail.com Subject: Re: [PATCH v8 1/2] dt-bindings: Documentation for qcom, llcc Message-ID: <20180622170758.GH10336@builder> References: <1527122121-31452-1-git-send-email-rishabhb@codeaurora.org> <1527122121-31452-2-git-send-email-rishabhb@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1527122121-31452-2-git-send-email-rishabhb@codeaurora.org> User-Agent: Mutt/1.9.5 (2018-04-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed 23 May 17:35 PDT 2018, Rishabh Bhatnagar wrote: > Documentation for last level cache controller device tree bindings, > client bindings usage examples. > > Signed-off-by: Channagoud Kadabi > Signed-off-by: Rishabh Bhatnagar > Reviewed-by: Evan Green > Reviewed-by: Rob Herring Reviewed-by: Bjorn Andersson Regards, Bjorn > --- > .../devicetree/bindings/arm/msm/qcom,llcc.txt | 26 ++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt > > diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt > new file mode 100644 > index 0000000..5e85749 > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt > @@ -0,0 +1,26 @@ > +== Introduction== > + > +LLCC (Last Level Cache Controller) provides last level of cache memory in SOC, > +that can be shared by multiple clients. Clients here are different cores in the > +SOC, the idea is to minimize the local caches at the clients and migrate to > +common pool of memory. Cache memory is divided into partitions called slices > +which are assigned to clients. Clients can query the slice details, activate > +and deactivate them. > + > +Properties: > +- compatible: > + Usage: required > + Value type: > + Definition: must be "qcom,sdm845-llcc" > + > +- reg: > + Usage: required > + Value Type: > + Definition: Start address and the the size of the register region. > + > +Example: > + > + cache-controller@1100000 { > + compatible = "qcom,sdm845-llcc"; > + reg = <0x1100000 0x250000>; > + }; > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project >