Re: [PATCH v4 1/5] mtd: rawnand: denali_dt: set clk_x_rate to 200 MHz unconditionally

Boris Brezillon
2018-06-22T16:50:03Z

On Sat, 23 Jun 2018 01:06:34 +0900
Masahiro Yamada <yamada.masahiro@socionext.com> wrote:

> Since commit 1bb88666775e ("mtd: nand: denali: handle timing parameters
> by setup_data_interface()"), denali_dt.c gets the clock rate from the
> clock driver. The driver expects the frequency of the bus interface
> clock, whereas the clock driver of SOCFPGA provides the core clock.
> Thus, the setup_data_interface() hook calculates timing parameters
> based on a wrong frequency.
>
> To make it work without relying on the clock driver, hard-code the clock
> frequency, 200MHz. This is fine for existing DT of UniPhier, and also
> fixes the issue of SOCFPGA because both platforms use 200 MHz for the
> bus interface clock.
>
> Fixes: 1bb88666775e ("mtd: nand: denali: handle timing parameters by setup_data_interface()")
> Cc: linux-stable <stable@vger.kernel.org> #4.14+
> Reported-by: Philipp Rosenberger <p.rosenberger@linutronix.de>
> Suggested-by: Boris Brezillon <boris.brezillon@bootlin.com>
> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
> Tested-by: Richard Weinberger <richard@nod.at>

Applied.

Thanks,

Boris

> ---
>
> Changes in v4:
> - split into a very simple patch for backport candiate
>
> drivers/mtd/nand/raw/denali_dt.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/nand/raw/denali_dt.c b/drivers/mtd/nand/raw/denali_dt.c
> index cfd33e6..5869e90 100644
> --- a/drivers/mtd/nand/raw/denali_dt.c
> +++ b/drivers/mtd/nand/raw/denali_dt.c
> @@ -123,7 +123,11 @@ static int denali_dt_probe(struct platform_device *pdev)
> if (ret)
> return ret;
>
> - denali->clk_x_rate = clk_get_rate(dt->clk);
> + /*
> + * Hardcode the clock rate for the backward compatibility.
> + * This works for both SOCFPGA and UniPhier.
> + */
> + denali->clk_x_rate = 200000000;
>
> ret = denali_init(denali);
> if (ret)