From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7391AC43144 for ; Mon, 25 Jun 2018 12:34:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3726123CD7 for ; Mon, 25 Jun 2018 12:34:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3726123CD7 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bootlin.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933624AbeFYMem convert rfc822-to-8bit (ORCPT ); Mon, 25 Jun 2018 08:34:42 -0400 Received: from mail.bootlin.com ([62.4.15.54]:46658 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932246AbeFYMek (ORCPT ); Mon, 25 Jun 2018 08:34:40 -0400 Received: by mail.bootlin.com (Postfix, from userid 110) id DC72B20719; Mon, 25 Jun 2018 14:34:37 +0200 (CEST) Received: from xps13 (AAubervilliers-681-1-87-188.w90-88.abo.wanadoo.fr [90.88.29.188]) by mail.bootlin.com (Postfix) with ESMTPSA id 532D1203D9; Mon, 25 Jun 2018 14:34:37 +0200 (CEST) Date: Mon, 25 Jun 2018 14:34:37 +0200 From: Miquel Raynal To: Stefan Agner Cc: boris.brezillon@bootlin.com, dwmw2@infradead.org, computersforpeace@gmail.com, marek.vasut@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com, thierry.reding@gmail.com, dev@lynxeye.de, richard@nod.at, marcel@ziswiler.com, krzk@kernel.org, digetx@gmail.com, benjamin.lindqvist@endian.se, jonathanh@nvidia.com, pdeschrijver@nvidia.com, pgaikwad@nvidia.com, mirza.krak@gmail.com, gaireg@gaireg.de, linux-mtd@lists.infradead.org, linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v8 0/6] mtd: rawnand: add NVIDIA Tegra NAND flash support Message-ID: <20180625143437.24f71e7e@xps13> In-Reply-To: <20180624212727.21672-1-stefan@agner.ch> References: <20180624212727.21672-1-stefan@agner.ch> Organization: Bootlin X-Mailer: Claws Mail 3.15.0-dirty (GTK+ 2.24.31; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Stefan, On Sun, 24 Jun 2018 23:27:21 +0200, Stefan Agner wrote: > Eigth and hopefully final revision gets rid of nand_release() as > suggested by Boris. > > -- > Stefan > > Changes since v1: > - Split controller and NAND chip structure > - Add BCH support > - Allow to select algorithm and strength using device tree > - Improve HW ECC error reporting and use DEC_STATUS_BUF only > - Use SPDX license identifier > - Use per algorithm mtd_ooblayout_ops > - Use setup_data_interface callback for NAND timing configuration > > Changes since v2: > - Set clock rate using assigned-clocks > - Use BIT() macro > - Fix and improve timing calculation > - Improve ECC error handling > - Store OOB layout for tag area in Tegra chip structure > - Update/fix bindings > - Use more specific variable names (replace "value") > - Introduce nand-is-boot-medium > - Choose sensible ECC strenght automatically > - Use wait_for_completion_timeout > - Print register dump on completion timeout > - Unify tegra_nand_(read|write)_page in tegra_nand_page_xfer > > Changes since v3: > - Implement tegra_nand_(read|write)_raw using DMA > - Implement tegra_nand_(read|write)_oob using DMA > - Name registers according to Tegra 2 Technical Reference Manual (v02p) > - Use wait_for_completion_io_timeout to account for IO > - Get chip select id from device tree reg property > - Clear interrupts and reinit wait queues in case command/DMA times out > - Set default MTD name after nand_set_flash_node > - Move MODULE_DEVICE_TABLE after declaration of tegra_nand_of_match > - Make (rs|bch)_strength static > > Changes since v4: > - Pass OOB area to nand_check_erased_ecc_chunk > - Pass algorithm specific bits_per_step to tegra_nand_get_strength > - Store ECC layout in chip structure > - Fix pointer assignment (use NULL) > - Removed obsolete header delay.h > - Fixed newlines > - Use non-_io variant of wait_for_completion_timeout > > Changes since v5: > - Drop extra OOB bytes support > > Changes since v6: > - checkpatch.pl fixes > > Changes since v7: > - Replace nand_release() with mtd_device_unregister() + nand_cleanup() > > Lucas Stach (1): > ARM: dts: tegra: add Tegra20 NAND flash controller node > > Stefan Agner (5): > mtd: rawnand: add Reed-Solomon error correction algorithm > mtd: rawnand: add an option to specify NAND chip as a boot device > mtd: rawnand: tegra: add devicetree binding > mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver > ARM: dts: tegra: enable NAND flash on Colibri T20 > > .../devicetree/bindings/mtd/nand.txt | 6 +- > .../bindings/mtd/nvidia-tegra20-nand.txt | 64 + > MAINTAINERS | 7 + > arch/arm/boot/dts/tegra20-colibri-512.dtsi | 16 + > arch/arm/boot/dts/tegra20.dtsi | 15 + > drivers/mtd/nand/raw/Kconfig | 10 + > drivers/mtd/nand/raw/Makefile | 1 + > drivers/mtd/nand/raw/nand_base.c | 4 + > drivers/mtd/nand/raw/tegra_nand.c | 1230 +++++++++++++++++ > include/linux/mtd/rawnand.h | 7 + > 10 files changed, 1359 insertions(+), 1 deletion(-) > create mode 100644 Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt > create mode 100644 drivers/mtd/nand/raw/tegra_nand.c > Series applied to nand/next. I just changed the subject of patch3/6 to be "dt-bindings: mtd: add tegra NAND controller binding". Thanks, Miquèl