From: Rob Herring <robh@kernel.org>
To: Alexandre Belloni <alexandre.belloni@bootlin.com>
Cc: Wolfram Sang <wsa@the-dreams.de>,
Jarkko Nikula <jarkko.nikula@linux.intel.com>,
James Hogan <jhogan@kernel.org>,
Paul Burton <paul.burton@mips.com>,
Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
Mika Westerberg <mika.westerberg@linux.intel.com>,
linux-i2c@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-mips@linux-mips.org,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Allan Nielsen <allan.nielsen@microsemi.com>
Subject: Re: [PATCH 3/5] i2c: designware: add MSCC Ocelot support
Date: Fri, 20 Jul 2018 11:56:58 -0600 [thread overview]
Message-ID: <20180720175658.GA2930@rob-hp-laptop> (raw)
In-Reply-To: <20180717114837.21839-4-alexandre.belloni@bootlin.com>
On Tue, Jul 17, 2018 at 01:48:35PM +0200, Alexandre Belloni wrote:
> The Microsemi Ocelot I2C controller is a designware IP. It also has a
> second set of registers to allow tweaking SDA hold time and spike
> filtering.
>
> Cc: Rob Herring <robh+dt@kernel.org>
> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
> ---
> .../bindings/i2c/i2c-designware.txt | 5 ++++-
> drivers/i2c/busses/i2c-designware-core.h | 1 +
> drivers/i2c/busses/i2c-designware-platdrv.c | 20 +++++++++++++++++++
> 3 files changed, 25 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/i2c/i2c-designware.txt b/Documentation/devicetree/bindings/i2c/i2c-designware.txt
> index fbb0a6d8b964..7af4176da4af 100644
> --- a/Documentation/devicetree/bindings/i2c/i2c-designware.txt
> +++ b/Documentation/devicetree/bindings/i2c/i2c-designware.txt
> @@ -2,7 +2,7 @@
>
> Required properties :
>
> - - compatible : should be "snps,designware-i2c"
> + - compatible : should be "snps,designware-i2c" or "mscc,ocelot-i2c"
Sounds like the registers are optional (or could be initialized by
firmware), so shouldn't 'snps,designware-i2c' be a fallback compatible?
> - reg : Offset and length of the register set for the device
> - interrupts : <IRQ> where IRQ is the interrupt number.
>
> @@ -11,6 +11,9 @@ Recommended properties :
> - clock-frequency : desired I2C bus clock frequency in Hz.
>
> Optional properties :
> + - reg : for "mscc,ocelot-i2c", a second register set to configure the SDA hold
> + time, named ICPU_CFG:TWI_DELAY in the datasheet.
> +
> - i2c-sda-hold-time-ns : should contain the SDA hold time in nanoseconds.
> This option is only supported in hardware blocks version 1.11a or newer.
Perhaps this needs an update too? It sounds like Microsemi fixed this
problem on their own before version 1.11a of the IP block.
Rob
next prev parent reply other threads:[~2018-07-20 17:57 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-17 11:48 [PATCH 0/5] Add support for MSCC Ocelot i2c Alexandre Belloni
2018-07-17 11:48 ` [PATCH 1/5] i2c: designware: factorize setting SDA hold time Alexandre Belloni
2018-07-17 12:11 ` Andy Shevchenko
2018-07-17 12:31 ` Alexandre Belloni
2018-07-17 11:48 ` [PATCH 2/5] i2c: designware: allow IP specific sda_hold_time Alexandre Belloni
2018-07-17 14:33 ` Andy Shevchenko
2018-07-17 11:48 ` [PATCH 3/5] i2c: designware: add MSCC Ocelot support Alexandre Belloni
2018-07-17 12:19 ` Andy Shevchenko
2018-07-17 12:40 ` Alexandre Belloni
2018-07-17 15:16 ` Andy Shevchenko
2018-07-17 15:26 ` Andy Shevchenko
2018-07-20 17:56 ` Rob Herring [this message]
2018-07-17 11:48 ` [PATCH 4/5] mips: dts: mscc: Add i2c on ocelot Alexandre Belloni
2018-07-17 11:48 ` [PATCH 5/5] mips: dts: mscc: enable i2c on ocelot_pcb123 Alexandre Belloni
2018-07-17 12:21 ` [PATCH 0/5] Add support for MSCC Ocelot i2c Andy Shevchenko
2018-07-17 12:46 ` Alexandre Belloni
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