Re: [PATCH 0/2] x86/intel_rdt and perf/x86: Fix lack of coordination with perf

Reinette Chatre
2018-08-02T16:44:15Z

On 8/2/2018 9:18 AM, Peter Zijlstra wrote:
> On Thu, Aug 02, 2018 at 09:14:10AM -0700, Reinette Chatre wrote:
>
>> The current implementation does not coordinate with perf and this is
>> what I am trying to fix in this series.
>>
>> I do respect your NAK but it is not clear to me how to proceed after
>> obtaining it. Could you please elaborate on what you would prefer as a
>> solution to ensure accurate measurement of cache-locked data that is
>> better integrated?
>
> We have an in-kernel interface to perf, use that if you want access to
> the PMU. You will not directly stomp on PMU registers.

I do not see how I can do so without incurring the cache hits and misses
from the data needed and instructions run by this interface. Could you
please share how I can do so and still obtain the accurate measurement
of cache residency of a specific memory region?

Reinette