Re: [PATCH 0/2] x86/intel_rdt and perf/x86: Fix lack of coordination with perf

Peter Zijlstra
2018-08-02T19:54:27Z

On Thu, Aug 02, 2018 at 11:18:01AM -0700, Dave Hansen wrote:
> On 08/02/2018 10:37 AM, Peter Zijlstra wrote:
> >> I do not see how I can do so without incurring the cache hits and misses
> >> from the data needed and instructions run by this interface. Could you
> >> please share how I can do so and still obtain the accurate measurement
> >> of cache residency of a specific memory region?
> > That's the best you're going to get. You do _NOT_ get to use raw PMU.
>
> Hi Peter,
>
> This code is really fidgety. It's really easily perturbed even by tiny
> things like implicit cache accesses from the page walker filling the TLB
> from the page tables.
>
> Adding a bunch more code in the way is surely going to make it more
> fragile and imprecise.
>
> I totally understand not wanting to fill the tree with code hijacking
> the raw PMU. Is your reaction to this really around not wanting to
> start down the slippery slope that ends up with lots of raw PMU "owners"?

That and the fact that multiple owner directly contradicts what perf set
out to do, provide resource arbitration for the PMU.

Not being able to use both perf and this resctl thing at the same time
is utter crap. You will not get special dispensation.