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[217.229.28.128]) by smtp.gmail.com with ESMTPSA id j9-v6sm7526973wrv.5.2018.08.09.06.52.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Aug 2018 06:52:17 -0700 (PDT) Date: Thu, 9 Aug 2018 15:52:16 +0200 From: Thierry Reding To: Aapo Vienamo Cc: Ulf Hansson , Rob Herring , Mark Rutland , Jonathan Hunter , Adrian Hunter , Mikko Perttunen , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 5/8] arm64: dts: tegra186: Add SDMMC4 DQS trim value Message-ID: <20180809135216.GF21639@ulmo> References: <1533650404-18125-1-git-send-email-avienamo@nvidia.com> <1533650404-18125-6-git-send-email-avienamo@nvidia.com> <20180809114922.GN21639@ulmo> <20180809150226.64657f56@dhcp-10-21-25-168> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="py13wRIzy9nU46ee" Content-Disposition: inline In-Reply-To: <20180809150226.64657f56@dhcp-10-21-25-168> User-Agent: Mutt/1.10.0 (2018-05-17) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --py13wRIzy9nU46ee Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Aug 09, 2018 at 03:02:26PM +0300, Aapo Vienamo wrote: > On Thu, 9 Aug 2018 13:49:22 +0200 > Thierry Reding wrote: >=20 > > On Tue, Aug 07, 2018 at 05:00:01PM +0300, Aapo Vienamo wrote: > > > Add the HS400 DQS trim value for Tegra186 SDMMC4. > > >=20 > > > Signed-off-by: Aapo Vienamo > > > --- > > > arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 + > > > 1 file changed, 1 insertion(+) > > >=20 > > > diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/bo= ot/dts/nvidia/tegra186.dtsi > > > index 6e9ef26..9e07bc6 100644 > > > --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi > > > +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi > > > @@ -313,6 +313,7 @@ > > > nvidia,pad-autocal-pull-down-offset-1v8-timeout =3D <0x0a>; > > > nvidia,default-tap =3D <0x5>; > > > nvidia,default-trim =3D <0x9>; > > > + nvidia,dqs-trim =3D <63>; > > > status =3D "disabled"; > > > }; > > > =20 > >=20 > > Isn't this technically dependent on the board layout and as such would > > belong in the board DTS file? Or does this value work on all existing > > Tegra186 platforms? >=20 > This value is specified as part of the controller initialization > sequence in the TRM. I've understood that this (and other tap and trim) > value(s) are used for compensating the propagation delay differences > that are caused by the internal SoC layout. Hmm... it would seem to me like the routing on a board would have a more significant impact than the SoC internal routing. But perhaps the board- specific routing is actually what the automatic calibration is used for? Anyway, if it ever turns out that we need slightly different values on a given board, we can always override the value in the board DTS file. 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