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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id m11-v6sm16795014oif.27.2018.08.20.12.49.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 20 Aug 2018 12:49:07 -0700 (PDT) Date: Mon, 20 Aug 2018 14:49:06 -0500 From: Rob Herring To: Jolly Shah Cc: matthias.bgg@gmail.com, andy.gross@linaro.org, shawnguo@kernel.org, geert+renesas@glider.be, bjorn.andersson@linaro.org, sean.wang@mediatek.com, m.szyprowski@samsung.com, michal.simek@xilinx.com, mark.rutland@arm.com, rajanv@xilinx.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rajan Vaja , Jolly Shah Subject: Re: [PATCH v2 1/3] dt-bindings: soc: Add ZynqMP PM bindings Message-ID: <20180820194906.GB26783@bogus> References: <1534446483-12156-1-git-send-email-jollys@xilinx.com> <1534446483-12156-2-git-send-email-jollys@xilinx.com> <20180820194057.GA21738@bogus> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20180820194057.GA21738@bogus> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Aug 20, 2018 at 02:40:57PM -0500, Rob Herring wrote: > On Thu, Aug 16, 2018 at 12:08:01PM -0700, Jolly Shah wrote: > > From: Rajan Vaja > > > > Add documentation to describe Xilinx ZynqMP power management > > bindings. > > > > Signed-off-by: Rajan Vaja > > Signed-off-by: Jolly Shah > > --- > > .../bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt | 16 ++++++++++++++++ Also, this should be located in bindings/power/reset/ > > 1 file changed, 16 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt > > index d215d15..cb9a6b7 100644 > > --- a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt > > +++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt > > @@ -64,6 +64,17 @@ Output clocks are registered based on clock information received > > from firmware. Output clocks indexes are mentioned in > > include/dt-bindings/clock/xlnx,zynqmp-clk.h. > > > > +-------------------------------------------------------------------- > > +Device Tree Bindings for the Xilinx Zynq MPSoC Power Management > > +-------------------------------------------------------------------- > > +The zynqmp-power node describes the power management configurations. > > +It will control remote suspend/shutdown interfaces. > > + > > +Required properties: > > + - compatible: Must contain: "xlnx,zynqmp-power" > > + - interrupt-parent: Interrupt controller the interrupt is routed through > > interrupt-parent is implied and could be in a parent node, so remove. > > With that, > > Reviewed-by: Rob Herring > > > + - interrupts: Interrupt specifier > > + > > ------- > > Example > > ------- > > @@ -78,5 +89,10 @@ firmware { > > clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>; > > clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk"; > > }; > > + zynqmp_power: zynqmp-power { > > + compatible = "xlnx,zynqmp-power"; > > + interrupt-parent = <&gic>; > > + interrupts = <0 35 4>; > > + }; > > }; > > }; > > -- > > 2.7.4 > >