From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=3.0 tests=DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS,T_DKIM_INVALID, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07B21C433F4 for ; Fri, 24 Aug 2018 20:02:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id ADF7B2150F for ; Fri, 24 Aug 2018 20:02:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="lyNVjkEi"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="Wor0wLMu" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org ADF7B2150F Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727837AbeHXXih (ORCPT ); Fri, 24 Aug 2018 19:38:37 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:49848 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727720AbeHXXid (ORCPT ); Fri, 24 Aug 2018 19:38:33 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 3115D607C6; Fri, 24 Aug 2018 20:02:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1535140949; bh=uhcitaixr6k/dX3K1D99aQGT5y5QC+4xZm6B0nyvEVE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lyNVjkEiKnuoG7yPKqbo9bSsE/HNTtXyJHsIFVnfQ5XocYfuWwzX1NW6lFb1h376p apZrp7U0Ab7XbxxEocpjBbl7QYYch4SnjSoRY8J2BZhU6Xzn4O5D6SaMTWASsD7TfD 1I/UJoWg/wva15iu78LqU01GLHySqD3rQMdG16Pg= Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 09AEE60541; Fri, 24 Aug 2018 20:02:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1535140948; bh=uhcitaixr6k/dX3K1D99aQGT5y5QC+4xZm6B0nyvEVE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Wor0wLMuDpKB06O8UhdnY+rYyCdf2AG0058Tt0NnBTFo5ywh+otbwqNkVRQ8ZJqjS zQYt3lYmZffzuDUNe3s4DPH5wckfgUV5ByKsh/QxBiGX+oKtRkSTv8vvVGBifUyFVR vhMrizGwmUMn6PQSdjYtTcui2RZkBUrkRHS5i2pE= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 09AEE60541 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: marc.zyngier@arm.com, bjorn.andersson@linaro.org, sboyd@kernel.org, evgreen@chromium.org, linus.walleij@linaro.org Cc: rplsssn@codeaurora.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, rnayak@codeaurora.org, devicetree@vger.kernel.org, andy.gross@linaro.org, dianders@chromium.org, Lina Iyer Subject: [PATCH v2 5/5] arm64: dts: qcom: add wake up interrupts for GPIOs for SDM845 Date: Fri, 24 Aug 2018 14:01:57 -0600 Message-Id: <20180824200157.9993-6-ilina@codeaurora.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180824200157.9993-1-ilina@codeaurora.org> References: <20180824200157.9993-1-ilina@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org GPIOs that are wakeup capable have interrupt lines that are routed to the always-on interrupt controller (PDC) in parallel to the pinctrl. The interrupts listed here are the wake up lines corresponding to GPIOs. Signed-off-by: Lina Iyer --- Changes in v2: - Define IRQ trigger type in DT Changes in v1: - Use interrupt-extended for all TLMM interrupts - Define GPIO-PDC map using interrupt-names --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 152 ++++++++++++++++++++++++++- 1 file changed, 151 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 0208f8557ffa..8d87794092b0 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -712,11 +712,161 @@ tlmm: pinctrl@3400000 { compatible = "qcom,sdm845-pinctrl"; reg = <0x03400000 0xc00000>; - interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + interrupts-extended = + <&intc GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 30 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 31 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 32 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 33 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 34 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 35 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 36 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 37 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 38 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 39 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 41 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 42 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 43 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 44 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 45 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 46 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 47 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 49 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 50 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 51 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 52 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 54 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 55 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 56 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 57 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 58 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 59 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 60 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 61 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 62 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 63 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 64 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 65 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 66 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 67 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 68 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 69 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 70 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 71 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 72 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 73 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 74 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 75 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 76 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 77 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 79 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 80 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 81 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 82 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 83 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 84 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 85 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 86 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 90 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 91 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 92 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 95 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 96 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 97 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 98 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 99 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 100 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 102 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 103 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 104 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 105 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 106 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 107 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 108 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "summary-irq", + "gpio1", + "gpio3", + "gpio5", + "gpio10", + "gpio11", + "gpio20", + "gpio22", + "gpio24", + "gpio26", + "gpio30", + "gpio32", + "gpio34", + "gpio36", + "gpio37", + "gpio38", + "gpio39", + "gpio40", + "gpio43", + "gpio44", + "gpio46", + "gpio48", + "gpio52", + "gpio53", + "gpio54", + "gpio56", + "gpio57", + "gpio58", + "gpio59", + "gpio60", + "gpio61", + "gpio62", + "gpio63", + "gpio64", + "gpio66", + "gpio68", + "gpio71", + "gpio73", + "gpio77", + "gpio78", + "gpio79", + "gpio80", + "gpio84", + "gpio85", + "gpio86", + "gpio88", + "gpio91", + "gpio92", + "gpio95", + "gpio96", + "gpio97", + "gpio101", + "gpio103", + "gpio104", + "gpio115", + "gpio116", + "gpio117", + "gpio118", + "gpio119", + "gpio120", + "gpio121", + "gpio122", + "gpio123", + "gpio124", + "gpio125", + "gpio127", + "gpio128", + "gpio129", + "gpio130", + "gpio132", + "gpio133", + "gpio145", + "gpio41", + "gpio89", + "gpio31", + "gpio49", + "gpio41", + "gpio89", + "gpio31", + "gpio49"; qup_i2c0_default: qup-i2c0-default { pinmux { -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project