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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id j16-v6sm1387516oib.42.2018.08.28.18.05.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 28 Aug 2018 18:05:00 -0700 (PDT) Date: Tue, 28 Aug 2018 20:05:00 -0500 From: Rob Herring To: Florian Fainelli Cc: linux-arm-kernel@lists.infradead.org, Mark Rutland , Ray Jui , Scott Branden , Jon Mason , "maintainer:BROADCOM IPROC ARM ARCHITECTURE" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , open list , andrew@lunn.ch, rmk+kernel@armlinux.org.uk Subject: Re: [PATCH v2 2/3] dt-bindings: net: dsa: Document B53 SRAB interrupts and registers Message-ID: <20180829010500.GA28253@bogus> References: <20180828175420.7992-1-f.fainelli@gmail.com> <20180828175420.7992-3-f.fainelli@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20180828175420.7992-3-f.fainelli@gmail.com> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Aug 28, 2018 at 10:54:19AM -0700, Florian Fainelli wrote: > Document the Broadcom roboswitch Switch Register Access Block interrupt > lines and additional register base addresses for port mux configuration > and SGMII status/configuration registers. > > Signed-off-by: Florian Fainelli > --- > .../devicetree/bindings/net/dsa/b53.txt | 23 +++++++++++++++++++ > 1 file changed, 23 insertions(+) > > diff --git a/Documentation/devicetree/bindings/net/dsa/b53.txt b/Documentation/devicetree/bindings/net/dsa/b53.txt > index 1811e1972a7a..5f1029e853b8 100644 > --- a/Documentation/devicetree/bindings/net/dsa/b53.txt > +++ b/Documentation/devicetree/bindings/net/dsa/b53.txt > @@ -46,6 +46,29 @@ Required properties: > "brcm,bcm6328-switch" > "brcm,bcm6368-switch" and the mandatory "brcm,bcm63xx-switch" > > +Required properties for BCM585xx/586xx/88312 SoCs: > + > + - reg: a total of 3 register base addresses, the first one must be the > + Switch Register Access block base, the second is the port 5/4 mux > + configuration register and the third one is the SGMII configuration > + and status register base address. > + > + - interrupts: a total of 13 interrupts must be specified, in the following > + order: port 0-5, 7-8 link status change, then the integrated PHY interrupt, > + then the timestamping interrupt and the sleep timer interrupts for ports > + 5,7,8. Bulleted lists would be easier to read. > + > +Optional properties for BCM585xx/586xx/88312 SoCs: > + > + - reg-names: a total of 3 names matching the 3 base register address, must > + be "srab", "mux_config" and "sgmii_config"; Here too, one per line please. > + > + - interrupt-names: a total of 13 names matching the 13 interrupts specified > + must be: "link_state_p0", "link_state_p1", "link_state_p2", > + "link_state_p3", "link_state_p4", "link_state_p5", "link_state_p7", > + "link_state_p8", "phy", "ts", "imp_sleep_timer_p5", "imp_sleep_timer_p7", > + "imp_sleep_timer_p8" > + > See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional > required and optional properties. > > -- > 2.17.1 >