From: Jacob Pan <jacob.jun.pan@intel.com>
To: Lu Baolu <baolu.lu@linux.intel.com>
Cc: "Tian, Kevin" <kevin.tian@intel.com>,
Joerg Roedel <joro@8bytes.org>,
David Woodhouse <dwmw2@infradead.org>,
"Raj, Ashok" <ashok.raj@intel.com>,
"Kumar, Sanjay K" <sanjay.k.kumar@intel.com>,
"Liu, Yi L" <yi.l.liu@intel.com>,
"Sun, Yi Y" <yi.y.sun@intel.com>,
"peterx@redhat.com" <peterx@redhat.com>,
Jean-Philippe Brucker <jean-philippe.brucker@arm.com>,
"iommu@lists.linux-foundation.org"
<iommu@lists.linux-foundation.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Jacob Pan <jacob.jun.pan@linux.intel.com>,
jacob.jun.pan@intel.com
Subject: Re: [PATCH v2 02/12] iommu/vt-d: Manage scalalble mode PASID tables
Date: Thu, 6 Sep 2018 16:43:17 -0700 [thread overview]
Message-ID: <20180906164317.786bbdda@jacob-builder> (raw)
In-Reply-To: <44298d5c-5720-a382-07d1-a90a072ff24b@linux.intel.com>
On Thu, 6 Sep 2018 10:46:03 +0800
Lu Baolu <baolu.lu@linux.intel.com> wrote:
> >> @@ -224,7 +271,14 @@ struct pasid_entry
> >> *intel_pasid_get_entry(struct device *dev, int pasid)
> >> */
> >> static inline void pasid_clear_entry(struct pasid_entry *pe)
> >> {
> >> - WRITE_ONCE(pe->val, 0);
> >> + WRITE_ONCE(pe->val[0], 0);
> >> + WRITE_ONCE(pe->val[1], 0);
> >> + WRITE_ONCE(pe->val[2], 0);
> >> + WRITE_ONCE(pe->val[3], 0);
> >> + WRITE_ONCE(pe->val[4], 0);
> >> + WRITE_ONCE(pe->val[5], 0);
> >> + WRITE_ONCE(pe->val[6], 0);
> >> + WRITE_ONCE(pe->val[7], 0);
> >
> > memset?
>
> The order is important here. Otherwise, the PRESENT bit of this pasid
> entry might still set while other fields contains invalid values.
WRITE_ONCE/READ_ONCE will switch to __builtin_memcpy() in if the size
exceeds word size, ie. 64bit in this case. I don;t think compiler will
reorder built-in function. Beside, we only need to clear present and
FDP bit, right?
next prev parent reply other threads:[~2018-09-06 23:41 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-30 1:35 [PATCH v2 00/12] iommu/vt-d: Add scalable mode support Lu Baolu
2018-08-30 1:35 ` [PATCH v2 01/12] iommu/vt-d: Enumerate the scalable mode capability Lu Baolu
2018-09-06 1:55 ` Tian, Kevin
2018-09-06 2:25 ` Lu Baolu
2018-08-30 1:35 ` [PATCH v2 02/12] iommu/vt-d: Manage scalalble mode PASID tables Lu Baolu
2018-09-06 2:14 ` Tian, Kevin
2018-09-06 2:46 ` Lu Baolu
2018-09-06 2:52 ` Tian, Kevin
2018-09-06 3:05 ` Lu Baolu
2018-09-06 23:43 ` Jacob Pan [this message]
2018-09-07 1:57 ` Lu Baolu
2018-08-30 1:35 ` [PATCH v2 03/12] iommu/vt-d: Move page table helpers into header Lu Baolu
2018-09-06 2:15 ` Tian, Kevin
2018-09-06 2:52 ` Lu Baolu
2018-08-30 1:35 ` [PATCH v2 04/12] iommu/vt-d: Add 256-bit invalidation descriptor support Lu Baolu
2018-09-06 2:39 ` Tian, Kevin
2018-09-07 2:11 ` Lu Baolu
2018-08-30 1:35 ` [PATCH v2 05/12] iommu/vt-d: Reserve a domain id for FL and PT modes Lu Baolu
2018-08-30 1:35 ` [PATCH v2 06/12] iommu/vt-d: Add second level page table interface Lu Baolu
2018-09-06 3:11 ` Tian, Kevin
2018-09-07 2:47 ` Lu Baolu
2018-09-07 17:43 ` Raj, Ashok
2018-09-13 5:52 ` Tian, Kevin
2018-08-30 1:35 ` [PATCH v2 07/12] iommu/vt-d: Setup pasid entry for RID2PASID support Lu Baolu
2018-08-30 1:35 ` [PATCH v2 08/12] iommu/vt-d: Pass pasid table to context mapping Lu Baolu
2018-09-06 3:17 ` Tian, Kevin
2018-09-07 2:13 ` Lu Baolu
2018-08-30 1:35 ` [PATCH v2 09/12] iommu/vt-d: Setup context and enable RID2PASID support Lu Baolu
2018-08-30 1:35 ` [PATCH v2 10/12] iommu/vt-d: Add first level page table interface Lu Baolu
2018-08-30 1:35 ` [PATCH v2 11/12] iommu/vt-d: Shared virtual address in scalable mode Lu Baolu
2018-08-30 1:35 ` [PATCH v2 12/12] iommu/vt-d: Remove deferred invalidation Lu Baolu
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