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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id m20-v6sm38496384pfg.61.2018.09.10.10.44.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 10 Sep 2018 10:44:25 -0700 (PDT) Date: Mon, 10 Sep 2018 10:44:23 -0700 From: Bjorn Andersson To: Douglas Anderson Cc: Andy Gross , swboyd@chromium.org, tfiga@chromium.org, Manu Gautam , David Collins , Vivek Gautam , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , David Brown , Mark Rutland , linux-soc@vger.kernel.org Subject: Re: [PATCH v3 1/3] arm64: dts: qcom: sdm845: Add USB-related nodes Message-ID: <20180910174423.GA2523@minitux> References: <20180822173629.202885-1-dianders@chromium.org> <20180822173629.202885-2-dianders@chromium.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20180822173629.202885-2-dianders@chromium.org> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed 22 Aug 10:36 PDT 2018, Douglas Anderson wrote: > From: Manu Gautam > > This adds nodes for USB and related PHYs. > > Signed-off-by: Manu Gautam > [dianders: reworked quite a bit] > Signed-off-by: Douglas Anderson Reviewed-by: Bjorn Andersson > --- > > Changes in v3: > - Don't just fix qfprom unit address, fix the reg too (Stephen). > - Rebased to next-20180822 > > Changes in v2: > - Use "0x784000" for qfprom rather than "0x780000" as per docs. > - Add calibration for 2nd USB port too > > arch/arm64/boot/dts/qcom/sdm845.dtsi | 196 +++++++++++++++++++++++++++ > 1 file changed, 196 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi > index 627e8c181c20..8c2088de3a8d 100644 > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > @@ -8,6 +8,7 @@ > #include > #include > #include > +#include > #include > > / { > @@ -249,6 +250,23 @@ > #power-domain-cells = <1>; > }; > > + qfprom@784000 { > + compatible = "qcom,qfprom"; > + reg = <0x784000 0x8ff>; > + #address-cells = <1>; > + #size-cells = <1>; > + > + qusb2p_hstx_trim: hstx-trim-primary@1eb { > + reg = <0x1eb 0x1>; > + bits = <1 4>; > + }; > + > + qusb2s_hstx_trim: hstx-trim-secondary@1eb { > + reg = <0x1eb 0x2>; > + bits = <6 4>; > + }; > + }; > + > qupv3_id_0: geniqup@8c0000 { > compatible = "qcom,geni-se-qup"; > reg = <0x8c0000 0x6000>; > @@ -962,6 +980,184 @@ > }; > }; > > + usb_1_hsphy: phy@88e2000 { > + compatible = "qcom,sdm845-qusb2-phy"; > + reg = <0x88e2000 0x400>; > + status = "disabled"; > + #phy-cells = <0>; > + > + clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, > + <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "cfg_ahb", "ref"; > + > + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; > + > + nvmem-cells = <&qusb2p_hstx_trim>; > + }; > + > + usb_2_hsphy: phy@88e3000 { > + compatible = "qcom,sdm845-qusb2-phy"; > + reg = <0x88e3000 0x400>; > + status = "disabled"; > + #phy-cells = <0>; > + > + clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, > + <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "cfg_ahb", "ref"; > + > + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; > + > + nvmem-cells = <&qusb2s_hstx_trim>; > + }; > + > + usb_1_qmpphy: phy@88e9000 { > + compatible = "qcom,sdm845-qmp-usb3-phy"; > + reg = <0x88e9000 0x18c>, > + <0x88e8000 0x10>; > + reg-names = "reg-base", "dp_com"; > + status = "disabled"; > + #clock-cells = <1>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, > + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, > + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, > + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; > + clock-names = "aux", "cfg_ahb", "ref", "com_aux"; > + > + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, > + <&gcc GCC_USB3_PHY_PRIM_BCR>; > + reset-names = "phy", "common"; > + > + usb_1_ssphy: lane@88e9200 { > + reg = <0x88e9200 0x128>, > + <0x88e9400 0x200>, > + <0x88e9c00 0x218>, > + <0x88e9a00 0x100>; > + #phy-cells = <0>; > + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; > + clock-names = "pipe0"; > + clock-output-names = "usb3_phy_pipe_clk_src"; > + }; > + }; > + > + usb_2_qmpphy: phy@88eb000 { > + compatible = "qcom,sdm845-qmp-usb3-uni-phy"; > + reg = <0x88eb000 0x18c>; > + status = "disabled"; > + #clock-cells = <1>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, > + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, > + <&gcc GCC_USB3_SEC_CLKREF_CLK>, > + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; > + clock-names = "aux", "cfg_ahb", "ref", "com_aux"; > + > + resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, > + <&gcc GCC_USB3_PHY_SEC_BCR>; > + reset-names = "phy", "common"; > + > + usb_2_ssphy: lane@88eb200 { > + reg = <0x88eb200 0x128>, > + <0x88eb400 0x1fc>, > + <0x88eb800 0x218>, > + <0x88e9600 0x70>; > + #phy-cells = <0>; > + clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; > + clock-names = "pipe0"; > + clock-output-names = "usb3_uni_phy_pipe_clk_src"; > + }; > + }; > + > + usb_1: usb@a6f8800 { > + compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; > + reg = <0xa6f8800 0x400>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, > + <&gcc GCC_USB30_PRIM_MASTER_CLK>, > + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, > + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, > + <&gcc GCC_USB30_PRIM_SLEEP_CLK>; > + clock-names = "cfg_noc", "core", "iface", "mock_utmi", > + "sleep"; > + > + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, > + <&gcc GCC_USB30_PRIM_MASTER_CLK>; > + assigned-clock-rates = <19200000>, <150000000>; > + > + interrupts = , > + , > + , > + ; > + interrupt-names = "hs_phy_irq", "ss_phy_irq", > + "dm_hs_phy_irq", "dp_hs_phy_irq"; > + > + power-domains = <&gcc USB30_PRIM_GDSC>; > + > + resets = <&gcc GCC_USB30_PRIM_BCR>; > + > + usb_1_dwc3: dwc3@a600000 { > + compatible = "snps,dwc3"; > + reg = <0xa600000 0xcd00>; > + interrupts = ; > + snps,dis_u2_susphy_quirk; > + snps,dis_enblslpm_quirk; > + phys = <&usb_1_hsphy>, <&usb_1_ssphy>; > + phy-names = "usb2-phy", "usb3-phy"; > + }; > + }; > + > + usb_2: usb@a8f8800 { > + compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; > + reg = <0xa8f8800 0x400>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, > + <&gcc GCC_USB30_SEC_MASTER_CLK>, > + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, > + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, > + <&gcc GCC_USB30_SEC_SLEEP_CLK>; > + clock-names = "cfg_noc", "core", "iface", "mock_utmi", > + "sleep"; > + > + assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, > + <&gcc GCC_USB30_SEC_MASTER_CLK>; > + assigned-clock-rates = <19200000>, <150000000>; > + > + interrupts = , > + , > + , > + ; > + interrupt-names = "hs_phy_irq", "ss_phy_irq", > + "dm_hs_phy_irq", "dp_hs_phy_irq"; > + > + power-domains = <&gcc USB30_SEC_GDSC>; > + > + resets = <&gcc GCC_USB30_SEC_BCR>; > + > + usb_2_dwc3: dwc3@a800000 { > + compatible = "snps,dwc3"; > + reg = <0xa800000 0xcd00>; > + interrupts = ; > + snps,dis_u2_susphy_quirk; > + snps,dis_enblslpm_quirk; > + phys = <&usb_2_hsphy>, <&usb_2_ssphy>; > + phy-names = "usb2-phy", "usb3-phy"; > + }; > + }; > + > tsens0: thermal-sensor@c263000 { > compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; > reg = <0xc263000 0x1ff>, /* TM */ > -- > 2.18.0.1017.ga543ac7ca45-goog >